电路仿真

Circuit Simulation

电路模拟一直是重要的 DAC 主题，特别是与 IC 设计相关的主题。电路模拟在 IC 设计中的巨大成功一直是 EDA 行业诞生的主要推动力。IBM 研究人员是这些年来最突出的力量：Frank Branin 是确定电路模拟架构的先驱。在我看来，Brayton、Hachtel 和位于约克镇的 IBM TJ Watson 研究中心的同事为这一领域做出了根本性的革命性贡献：他们引入了我们今天所知的电路模拟背后的算法，从稀疏矩阵到后向微分公式。他们促成了两个重要程序的开发：IBM 的 Astap（高级统计分析程序）和加州大学伯克利分校的 Spice（集成电路重点模拟程序）。Ron Rohrer 和 Don Pederson 的早期贡献对于使这些程序成为多年来电路模拟的主力至关重要。

Circuit simulation has been an important DAC topic, especially as it relates to IC design. The great success of circuit simulation in IC designs has been a dominant driver in the birth of EDA as an industry. IBM researchers were the most prominent force in these years: Frank Branin was a pioneer in determining the architecture for circuit simulation. In my opinion, Brayton, Hachtel, and colleagues at IBM T.J. Watson Research Center in Yorktown made fundamental, revolutionary contributions to this field: They introduced the algorithms behind circuit simulation as we know it today, from sparse matrices to backward differentiation formulas. They enabled the development of two important programs: IBM's Astap (advanced statistical analysis program) and UC Berkeley's Spice (simulation program for integrated circuits emphasis). The early contributions of Ron Rohrer and Don Pederson were essential to making these programs the workhorses of circuit simulation for years and years.

逻辑仿真与测试

Logic Simulation and Testing

当 DAC 开始时，逻辑模拟已经投入使用一段时间了。IBM 和 CDC 等计算机公司依靠这项技术来调试他们的逻辑设计。对该领域的贡献不计其数，该领域的创始人在开发自动测试模式生成和故障模拟方面也发挥了重要作用。密歇根大学的 Ulrich 和 Hayes、南加州大学的 Breuer 和德克萨斯大学奥斯汀分校的 Szygenda 等人发挥了不可估量的作用。Tom Williams 及其同事发明了一种电平敏感扫描设计方法，IBM 的 Paul Roth 随后开发了 D 算法，改变了该行业设计计算机硬件和生成测试模式的方式。

Logic simulation had already been in use for some time when DAC started. Computer companies, such as IBM and CDC, relied on this technology to debug their logic designs. The contributions to this field are countless, and the field's founders also had a fundamental role in developing automatic test pattern generation and fault simulation. The role of Ulrich and Hayes at the University of Michigan; Breuer at the University of Southern California; and Szygenda at the University of Texas at Austin, to name a few, was invaluable. The invention of a methodology for level-sensitive scan design by Tom Williams and colleagues, and the consequent development of the D-algorithm by Paul Roth of IBM, changed the way in which this industry designed computer hardware and generated test patterns.

MOS 时序仿真

MOS Timing Simulation

利用 MOS 晶体管的准单向特性来加速电路仿真，最早出现在 1975 年 Gummel 和贝尔实验室同事的工作中。Gummel 的直觉是使用基于快速松弛的启发式算法来近似描述电路的常微分方程的解。他的洞察力是认识到，在分析数字电路的时序时，只要开关事件能够及时正确放置，其准确的波形并不重要。这一洞察力仍然是当今快速电路仿真的基础。

Exploiting the quasi-unidi-rectional characteristic of a MOS transistor to speed up circuit simulation first appeared in the work of Gummel and colleagues of Bell Labs in 1975. Gummel's intuition was to approximate the solution of the ordinary differential equations describing the circuits with a fast relaxation-based heuristic algorithm. His insight was to recognize that when analyzing a digital circuit's timing, its accurate waveforms are unimportant as long as the switching events could be correctly placed in time. This insight is still the basis of today's fast circuit simulation.

线路布线

Wire Routing

我们今天在工具中使用的大多数技术都是基于这一时期获得的结果。著名的 Lee 迷宫路由器于 1961 年（第一个 DAC 之前）开发，仍然是当今大多数路由器的基础。Hightower 线路扩展算法可以追溯到 1969 年，而通道路由的想法则来自 Hashimoto 和 Stevens 在 1971 年的工作。

Most of the techniques that we use today in our tools are based on the results obtained in this period. The famous Lee maze router developed in 1961 (before the first DAC), is still the basis for most of the routers in use today. The Hightower line extension algorithm dates back to 1969, and the idea of channel routing came from the work by Hashimoto and Stevens in 1971.

常规数组

Regular Arrays

随着大规模集成电路的出现，规则布局模式对于缩短设计时间的吸引力越来越大。研究人员开发了门阵列（在 IBM 称为主切片）和标准单元（在 IBM 称为主图像）作为自定义布局的替代方案。在此期间，IBM 和贝尔实验室广泛使用了集成工具，这些工具使用这些设计样式来自动布局电路。我记得这个想法的开始，当时一个门阵列集成电路有四个门，斯伦贝谢的一位研究人员讨论了使用自动化工具来优化电路的利用率。看看我们从那时起走过的路程：40 年来，单个芯片上的门数从 4 亿个增加到 4 亿个。

With the advent of large-scale ICs, the appeal of regular layout patterns for reducing design time was strong. Researchers developed gate arrays (called master slices at IBM) and standard cells (master images at IBM) as alternatives to custom layouts. In this period, IBM and Bell Labs made extensive use of integrated tools using these design styles for the automatic layout of circuits. I remember the beginning of this idea, when a gate array IC had four gates and a Schlumberger researcher discussed the use of automated tools to optimize the circuit's utilization. Look at the distance we've covered since then: in 40 years, from four to 400 million gates on a single chip.

验证和测试

Verification and Testing

这一领域包括两条主要工作路线。一条侧重于使电路仿真比 Spice 快几个数量级；另一条侧重于形式化技术，以证明电路能够正确运行。在第一个领域，Richard Newton、Albert Ruehli 和我等人在 1980 年左右对基于松弛的技术和混合模式仿真的研究为当今使用的快速 MOS 模拟器奠定了基础。Bryant 的其他工作侧重于数字电路的仿真，其速度比 Spice 快两个数量级，精度介于电路仿真和逻辑仿真之间。

This field encompassed two main lines of work. One focused on making circuit simulation orders of magnitude faster than with Spice; the other focused on formal techniques to prove that the circuit would perform correctly. In the first domain, the work on relaxation-based techniques and mixed-mode simulation by, among others, Richard Newton, Albert Ruehli, and myself around 1980, established the basis for the fast MOS simulators in use today. Other work by Bryant focused on the simulation of digital circuits with a two-order-of-magnitude speedup over Spice and accuracy between the one offered by circuit simulation and the one offered by logic simulation.

随着几何尺寸的缩小，互连的影响越来越大。1981 年，Penfield 和 Rubinstein 提出的互连延迟模型得到了广泛应用。卡内基梅隆大学的 Pileggi 和 Rohrer 着手解决互连模拟问题，并于 1988 年开发了渐近波形评估 (AWE) 方面的成果。

Interconnects had an increasing impact as geometries scaled down. The interconnect delay model introduced by Penfield and Rubinstein in 1981 saw extensive use. Pileggi and Rohrer at CMU tackled interconnect simulation, developing their results on asymptotic waveform evaluation (AWE) in 1988.

形式化技术最初旨在回答两个不同的门网络是否计算相同的布尔函数的问题。形式化验证的首次使用还是在 IBM 的 Bahnsen 时代，但这项工作从未出现在 DAC 论文集中。1986 年，Bryant 在二元决策图 (BDD) 方面的开创性工作通过引入布尔函数的规范形式和非常快速的操作算法彻底改变了该领域。Coudert 和 Madre 使用 BDD 进行有限状态机等价性的工作，以及 Ed Clarke、Ken McMillan、Dave Dill 和 Bob Kurshan 在 20 世纪 90 年代初进行模型检查的工作，将形式化验证提升到了更高的抽象层次。模型检查解决了验证由 FSM 表示的顺序系统是否满足描述为状态和转换上定义的逻辑命题的属性或另一个 FSM 的问题。

Formal techniques first aimed at answering the question of whether two different networks of gates computed the same Boolean function. The first use of formal verification was again at IBM by Bahnsen during the age of gods, but this work never appeared in the DAC proceedings. The seminal work by Bryant on binary decision diagrams (BDDs) in 1986 revolutionized the field by introducing a canonical form for Boolean functions and very fast manipulation algorithms. The work by Coudert and Madre on finite-state machine equivalence using BDDs, and the work by Ed Clarke, Ken McMillan, Dave Dill, and Bob Kurshan on model checking in the early 1990s, elevated formal verification to higher levels of abstraction. Model checking tackled the problem of verifying whether a sequential system represented by an FSM would satisfy a property described as a logic proposition defined on the states and transitions, or as another FSM.

在测试领域，著名的基于D算法的Podem-X计划于1981年在Prabhu Goel的指导下在IBM诞生。

In the testing area, the famous Podem-X program based on the D-algorithm emerged at IBM under the direction of Prabhu Goel in 1981.

布局

Layout

在表示和基本操作层面，艺术品编辑发生了根本性的变化。在前一个时期，设计师对每个设计步骤使用不同的数据存储库，并执行从一种数据格式到另一种数据格式的繁琐转换工作。20 世纪 80 年代初，牛顿在加州大学伯克利分校使用 Squid、Oct 和 VEM 的工作；以及奥斯特豪特使用 Magic 的工作，通过展示拥有统一数据库和图形用户界面的可能性，彻底改变了该领域。这项工作的影响不容小觑。OpenAccess 数据库借鉴了牛顿的开创性工作；一些高级物理设计的数据表示基于奥斯特豪特提出的角拼接思想。

At the representation and basic manipulation level, artwork editing saw a fundamental change. In the previous period, designers used different data repositories for each of the design steps and performed tedious translation work from one data format to another. In the early 1980s, Newton's work at UC Berkeley with Squid, Oct, and VEM; and Ousterhout's work with Magic revolutionized the field by showing that it was possible to have a unified database and graphical user interface. I cannot overemphasize the impact of this work. The OpenAccess database has borrowed from Newton's seminal work; some of the data representations for advanced physical design are based on the idea of corner stitching introduced by Ousterhout.

另一个革命性的想法源自硅片编译和布局语言的研究。几个研究小组大约在同一时间探索了这一领域。这些小组分别来自麻省理工学院 (Battali)、加州理工学院 (Mead 的团队和 Bristle Block 硅片编译器) 和贝尔实验室 (Gummel；Buric 及其同事和 L 布局语言)。这个想法是将计算机科学文化的某些部分注入 IC 设计中。尽管这种方法在智力上很优雅且功能强大，但目前的工具中几乎没有保留它。

Another revolutionary idea arose from work on silicon compilation and layout languages. Several research groups explored this area at around the same time. These groups were at MIT (Battali), Caltech (Mead's group with the Bristle Block silicon compiler), and Bell Labs (Gummel; Buric and colleagues with the L layout language). The idea was to inject IC design with some parts of the computer science culture. Although the approach was intellectually elegant and powerful, little of it remains in present tools.

两位物理学家 Kirkpatrick 和 Gelatt 利用他们的物理知识开发了模拟退火算法，并于 1980 年在 IBM 引入该算法来解决门阵列布局的布局问题。这种方法一经公布，便引发了大量关于其有效实施和理论特性的研究。该算法针对标准单元和宏单元布局以及全局布线进行了定制。从英特尔到 DEC，从摩托罗拉到 TI，大多数大公司都使用了加州大学伯克利分校 Sechen 编写的 TimberWolf 系统。

Two physicists, Kirkpatrick and Gelatt, used their knowledge of physics to develop simulated annealing, introducing it at IBM in 1980 to solve a placement problem for gate array layout. Once publicized, this approach gave rise to a great deal of research on its efficient implementation and theoretical properties. Customizations of the algorithm took place for standardcell and macrocell layout as well as for global routing. Most of the major companies, from Intel to DEC, and from Motorola to TI, used the TimberWolf system written by Sechen at UC Berkeley.

这些年，理论计算机科学家也对研究布局设计的组合方面产生了浓厚的兴趣。Rivest 和 Pinter（麻省理工学院）在布线方面的工作，以及 Karp（加州大学伯克利分校）在布局和布线方面的工作就是这种参与的典型例子。这清楚地表明 EDA 成功地吸引了其他社区的参与。在此期间，加州大学伯克利分校的 Kuh 的工作产生了用于宏单元设计的集成布局系统和用于布局和布线的点工具；这些系统对该领域产生了巨大影响。

These years also witnessed significant interest from theoretical computer scientists about studying the combinatorial aspects of layout design. The work of Rivest and Pinter (MIT) on routing, and of Karp (UC Berkeley) on placement and routing, were examples of this involvement. This was a clear sign of EDA's success in attracting other communities to contribute. During this time, the work of Kuh at UC Berkeley yielded integrated layout systems for macrocell design and point tools for placement and routing; these systems had a great impact on the field.

逻辑综合

Logic Synthesis

1979 年，Darringer、Joyner 和 Trevillyan 发表了一篇开创性的论文，介绍了逻辑综合。这些研究人员使用基于窥孔规则的优化来生成设计的高效门级表示。紧接着这项工作，IBM 于 1979 年独立地开始了另一种布尔优化方法。Brayton 和 Hachtel 与加州大学伯克利分校的 Newton 和我合作开发了两级逻辑优化器 Espresso 和两个多级逻辑优化器，即 Yorktown Silicon Compiler 和多级交互式综合 (MIS) 系统。这项工作得到了国防高级研究计划局 (DARPA) 的支持，历时 10 多年。在 MIS 的早期开发中，它包含一个技术独立的阶段，用于操纵和优化布尔函数，然后是技术映射步骤，将优化的布尔函数映射到门库。所有大公司（英特尔、ST、TI、摩托罗拉、霍尼韦尔、DEC 和飞利浦）很快都采用了该版本的 MIS。

A seminal paper by Darringer, Joyner, and Trevillyan introduced logic synthesis in 1979. These researchers used peephole rule-based optimization to generate efficient gate-level representations of a design. Immediately following this work and somewhat independently, another approach to Boolean optimization began at IBM in 1979. Brayton and Hachtel, in collaboration with Newton and me at UC Berkeley, developed the two-level logic optimizer Espresso, and two multilevel logic optimizers, the Yorktown Silicon Compiler and the Multilevel Interactive Synthesis (MIS) system. This work, supported by the Defense Advanced Research Projects Agency (DARPA), spanned more than 10 years. In MIS’ early development, it incorporated a technology-independent phase that manipulated and optimized Boolean functions, followed by a technology-mapping step that mapped the optimized Boolean functions to a library of gates. All the major companies—Intel, ST, TI, Motorola, Honeywell, DEC, and Philips—soon adopted this version of MIS.

在第二阶段，常见的方法是使用基于规则的技术，例如通用电气的 Aart DeGeus 及其同事开发的 Socrates 系统中的技术。Kurt Keutzer 后来展示了如何使用 Aho 和 Ullman 的编译器工作来获得高效的技术映射器。这个想法是将技术映射表述为一个树覆盖问题，并用动态规划来解决。这个想法在当今的大多数逻辑综合系统中仍然适用。日本富士通、NTT 和 NEC 的工作非常出色，他们主要基于 IBM 的 Darringer 的原创工作来制作有效的逻辑综合系统。

In the second phase, the common approach was to use rule-based techniques like those in the Socrates system, developed at General Electric by Aart DeGeus and colleagues. Kurt Keutzer later showed how to use the compiler work by Aho and Ullman to obtain a highly efficient technology mapper. The idea was to formulate technology mapping as a tree-covering problem to be solved with dynamic programming. This idea still finds a home in most of today's logic synthesis systems. The work in Japan at Fujitsu, NTT, and NEC was outstanding in producing working logic synthesis systems based primarily on the original work of Darringer at IBM.

逻辑综合是我们社区的一大成就，因此，它是许多论文的来源，并引起了其他相关领域的极大兴趣。在 1985 年国际测试大会的主题演讲中，我断言测试模式生成和逻辑综合确实是同一枚硬币的两个面。Keutzer、Devadas、Malik、McGeer 和 Saldanha 与 Brayton、Newton 和我合作完成的工作展示了使用逻辑综合技术进行冗余消除和延迟测试的几个结果。V. Agrawal、Tim Cheng 等人的新测试算法源于这两个领域的交叉融合。

Logic synthesis was a great achievement of our community, and as such, it was the source of many papers and attracted significant interest from those in other connected fields. In a keynote address at the International Test Conference in 1985, I asserted that test pattern generation and logic synthesis were indeed two faces of the same coin. The work by Keutzer, Devadas, Malik, McGeer, and Saldanha in collaboration with Brayton, Newton, and me demonstrated several results in redundancy removal and delay testing using logic synthesis techniques. New testing algorithms from V. Agrawal, Tim Cheng, and others arose from the cross-pollination of the two fields.

在逻辑综合的成熟时期，Coudert 和 Madre 能够通过使用 BDD 显著加速基于布尔函数的合取范式 (CNF) 表示的逻辑综合算法。

In the mature period of logic synthesis, Coudert and Madre were able to considerably accelerate logic synthesis algorithms based on conjunctive normal form (CNF) representations of Boolean functions by using BDDs.

硬件描述语言

Hardware Description Languages

逻辑综合这一技术工作更适合归类为逻辑优化，因为算法将数字电路的布尔表示转换为优化的等效表示。综合意味着在两个抽象层之间架起一座桥梁。硬件描述语言的诞生是为了比布尔函数更高效、更紧凑地表示数字电路。真正的综合工作是将 HDL 描述映射到门网络表中。不幸的是，HDL 的开发与逻辑优化工作无关。这意味着逻辑综合算法无法处理 HDL 的所有构造，例如 Verilog（由 Moorby 及其同事提出）和 VHDL。因此，有必要将这些语言的使用限制在其所谓的可综合子集内。尽管 HDL 在设计周期早期引入验证以缩短设计时间方面确实取得了很大进步，但子集化的需求表明 HDL 在语义方面存在问题。

The technical work characterized as logic synthesis would be better classified as logic optimization because the algorithms change a digital circuit's Boolean representation into an optimized equivalent representation. Synthesis implies a bridge between two layers of abstractions. Hardware description languages were born to more efficiently and compactly represent digital circuits than Boolean functions. The real synthesis job became mapping an HDL description into a netlist of gates. Unfortunately, HDL development began independently of the work on logic optimization. This implied that logic synthesis algorithms could not tackle all the constructs of HDLs such as Verilog (proposed by Moorby and colleagues) and VHDL. It thus became necessary to restrict the use of these languages to their so-called synthesizable subset. Although HDLs were indeed a great advance in terms of introducing verification early in the design cycle to reduce design time, the need for subsetting showed that HDLs had problems on the semantic side.

这些年来，HDL 之争非常有趣：Verilog 是一种专有语言（Gateway Design 销售 Verilog 模拟器并授权该语言），而 VHDL 是 DARPA 在 VHSIC 计划中支持的开放标准。我们这些从业者在 DAC 上就一种语言比另一种语言更优越进行了无数次辩论。当 Verilog 公开时，两者之间主要存在外观上的差异，尽管大多数人根据个人喜好表达了对其中一种或另一种的强烈喜爱。Joe Costello 非常雄辩地指出，为一项任务采用两种标准通常是一个坏主意：“……采用 VHDL 是设计自动化历史上最大的错误之一，导致用户和 EDA 供应商浪费了数亿美元……”

The HDL battle was very interesting during these years: Verilog was a proprietary language (Gateway Design was selling a Verilog simulator and licensed the language) while VHDL was an open standard supported by the DARPA within the VHSIC program. We practitioners had countless debates about the superiority of one language over the other at DAC. When Verilog became public, there were mostly cosmetic differences between the two, even though most people expressed a strong attachment to one or the other, according to their personal taste. Joe Costello very eloquently argued that the adoption of two standards for a single task is in general a bad idea: “ … Adoption of VHDL was one of the biggest mistakes in the history of design automation, causing users and EDA vendors to waste hundreds of millions of dollars…”

硬件加速

Hardware Acceleration

所有 EDA 方法都需要大量的计算时间来对非常大的数据集执行复杂的算法。在技术大发展时期，定制硬件来加速 EDA 算法的执行非常有吸引力。像往常一样，IBM（我相信它是对该领域影响最大的唯一机构）提出了一种用于逻辑模拟的专用架构，即 Pfister 及其同事的 Yorktown 模拟引擎 (YSE)。性能上的巨大优势推动了强劲的行业活动；企业家们成立了几家新公司来服务硬件加速市场。硬件加速的理念扩展到其他 EDA 领域，包括线路布线（通过 IBM 的 Ravi Nair 及其同事）。然而，它在其他领域没有足够的吸引力来复制 YSE 的成功。

All EDA approaches require a massive amount of compute time to execute complex algorithms on very large data sets. In a great expansion period for the technology, customized hardware to speed up the execution of EDA algorithms was extremely appealing. As usual, IBM (which I believe is the single institution with the most impact on this field) proposed a special-purpose architecture for logic simulation, the Yorktown Simulation Engine (YSE), by Pfister and colleagues. The great advantages in performance drove strong industry activity; entrepreneurs formed several new companies to serve the hardware acceleration market. The idea of hardware acceleration extended to other EDA fields, including wire routing (via Ravi Nair and colleagues at IBM). However, it did not have enough appeal in other areas to repeat the success of YSE.

与此同时，研究人员还寻求另一种思路，即使用通用并行计算机来实现类似的性能优势，但开发成本更低。20 世纪 80 年代末，计算机设计界对并行架构表现出浓厚的兴趣。Thinking Machines 采用由麻省理工学院的 Danny Hillis 设计的大规模并行架构，在研究和工业界（包括 EDA）引起了轰动。这家围绕这台机器成立的公司传播了这种计算方法，并吸引了该领域一些最优秀的人才。例如，诺贝尔奖获得者 Richard Feynman 设计并实现了处理器间通信的路由算法；他在 Thinking Machines 的厂房里花了很多时间。关于算法和应用的即兴辩论很常见；当时最杰出的科学家举办了研讨会。研究人员为这种架构开发了算法，包括用于电路和逻辑模拟以及布局和布线的算法。然而，由于缺乏对最终用户需要完整解决方案而不是强大硬件的理解，这些机器的工业用途仅限于研究实验室；这种情况最终导致了公司的倒闭。

In parallel with this work, researchers pursued the alternative idea of using general-purpose parallel computers to achieve similar performance advantages but at a lower development cost. In the late 1980s, the computer design community showed significant interest in parallel architectures. Thinking Machines, using a massively parallel architecture designed by Danny Hillis at MIT, generated excitement in research and industrial communities, including EDA. The company formed around this machine disseminated this approach to computing and attracted some of the very best minds in the field. For example, Nobel laureate Richard Feynman designed and implemented the routing algorithms for the communication among processors; he spent many hours on Thinking Machines' premises. Impromptu debates about algorithms and applications were common; the most prominent scientists of the time gave seminars. Researchers developed algorithms for this architecture, including those for circuit and logic simulation, and for placement and routing. However, the lack of understanding that final users needed complete solutions, rather than powerful hardware, limited the industrial use of these machines to research laboratories; this situation eventually led to the demise of the company.

在同一时期，EDA 中的其他人积极追求并使用并行架构，例如 N-cube、Sequent 和 Intel 超立方体。然而，到目前为止，还没有人出售基于这些机器的商业工具。我相信，具有不同程度异构性的并行计算仍然是 EDA 和其他工程应用的重要结果尚未开发的来源。然而，在并行计算得到广泛使用之前，研究人员必须解决软件支持的基本问题。

During the same time period, others in EDA actively pursued and used parallel architectures such as the N-cube, Sequent, and Intel hypercube. Up to now, however, no one has sold a commercial tool based on these machines. I believe that parallel computing with various degrees of heterogeneity is still an untapped source of important results for EDA and other engineering applications. Before parallel computing is of widespread use, however, researchers must solve the fundamental problem of software support.

高层设计

High-Level Design

高级或系统级设计是通向未来的桥梁。我们都同意，提高抽象级别对于将设计效率提高几个数量级至关重要。我确实对这个领域充满热情，我相信我们的未来取决于该领域的设计方法和工具的成功。基础工作（由 Thomas、Parker 和 Gajski 完成）始于 20 世纪 80 年代的高级综合。这项工作几乎与逻辑综合同时开始，研究人员开发了几种商业工具。尽管如此，设计界尚未广泛接受这种方法；仍有许多工作要做。

High- or system-level design is a bridge to the future. We all agree that raising the level of abstraction is essential to increasing design productivity by orders of magnitude. I am indeed very passionate about this field, and I believe our future rides on the success of design methodologies and tools in this area. The foundational work (by Thomas, Parker and Gajski) started in the 1980s with high-level synthesis. This work started almost in parallel with logic synthesis, and researchers developed several commercial tools. Despite these facts, the design community has not widely accepted this approach; much work remains to be done.

基本问题是，是什么让逻辑综合成功，又是什么让高级综合的采用如此困难？我认为，高级综合的原始工作过于笼统；设计人员不得不探索太多替代方案，而工具很难在这场游戏中击败人类。然而，当系统级设计专注于受限架构（如 DSP 和基于微处理器的架构）时，高级综合在行业中取得了一定程度的成功。DeMan 和 Rabaey 在 IMEC Cathedral 系统上的工作就是这一较窄领域成功的一个例子。系统中嵌入的硬件-软件协同设计方法（如斯坦福大学的 Vulcan、Paulin 的 Flex、布伦瑞克大学的 Cosyma 和加州大学伯克利分校的 Polis）是其他例子。

The basic question is what made logic synthesis successful, and what made the adoption of high-level synthesis so difficult? I believe that the original work on high-level synthesis was too general; designers had to explore too many alternatives, and the tools had a difficult time beating humans at this game. However, when system-level design focuses on constrained architectures such as DSPs and those based on microprocessors, high-level synthesis has had a degree of success in industry. The IMEC work by DeMan and Rabaey on the Cathedral system is one example of success in this narrower domain. Hardware-software codesign approaches embedded in systems—such as Vulcan at Stanford, Flex by Paulin, Cosyma at Braunschweig University, and Polis at UC Berkeley—are other examples.

在此期间，Ed Lee 开发了 Ptolemy，Harel 开发了 Statecharts，用于在算法层面进行设计捕获和验证；这项工作影响了当今嵌入式系统设计的方法。在软件设计方面，INRIA 的 Berry 和 Benveniste 以及 Verimag 的 Caspi 及其同事提出了同步语言（Esterel、Signal 和 Lustre）。

During this period, Ed Lee developed Ptolemy and Harel developed Statecharts for design capture and verification at the algorithmic level; this work influences present approaches to embedded-system design. In software design, Berry and Benveniste at INRIA, and Caspi and colleagues at Verimag have proposed synchronous languages (Esterel, Signal, and Lustre).

相关贡献

Relevant Contributions

关于这一时期的根本贡献，目前尚无定论。根据这一时期的特征，我不想在这里表明立场，将各种研究方法标记为成功或失败（现在下结论还为时过早），而只是对一些重要主题进行评论。我将把确定关键贡献的任务留给 10 年后发表主题演讲的演讲者！

The jury is still out as to the fundamental contributions of this period. In line with this period's characterization, I do not wish to take a position here by labeling various research approaches as successes or failures (it is simply too early to tell), but simply comment on some important topics. I will leave the task of identifying key contributions to the speaker delivering the keynote 10 years from now!

随着几何尺寸向亚微米范围迈进，物理验证已引起广泛关注。自测试已成为解决测试设备成本上升和要求提高的唯一解决方案。研究人员研究了异步设计方法和相关的综合问题，将其作为解决功耗限制和线路延迟不可预测性引起的性能问题的潜在解决方案。有意突破极限的设计师仍在努力应对深亚微米范式变化，寻找其极限以及收益是否值得冒这个险。随着芯片功能越来越多，模拟设计已成为瓶颈。在 SoC 中，游戏的名称已成为寻找模拟和数字组件之间的最佳匹配，而不是优化模拟部分的性能。由于模拟电路依赖于许多二阶效应，模拟设计更像是一门艺术而不是一门科学。我认为我们必须将科学纳入其中，使这项活动可重复且比现在快得多。

Physical verification has attracted much attention as geometries march toward the submicron range. Self-test has emerged as the only solution to rising costs and requirements for test equipment. Researchers have studied asynchronous design methods and the associated synthesis problem as potential solutions to performance problems arising from power consumption constraints and the unpredictability of wire delays. Designers interested in pushing the envelope still grapple with the deep-submicron paradigm change, seeking its limits and whether the gains are worth the approach's risks. As chips incorporate increasing functionality, analog design has become the bottleneck. In SoCs, the name of the game has become finding the best matches between analog and digital components, rather than optimizing the analog part's performance to death. Because of an analog circuit's dependency on many second-order effects, analog design has been more of an art than a science. I believe we must bring science into the picture to make this activity repeatable and much faster than it is today.

当布线延迟成为芯片设计中的重要问题时，使逻辑综合和布局分层成为可能的关注点分离开始在实现设计收敛方面遇到问题。也就是说，在逻辑级设计的电路在满足时序约束后很难满足这些约束。显然，无法实现设计收敛会导致不可接受的上市时间延迟和成本。今天提出的解决方案是将布局和逻辑综合（至少在门尺寸方面）合并为一个单一的优化循环。

When wiring delays became relevant in chip design, the separation of concerns that enabled the layering of logic synthesis and layout began having problems achieving design closure. That is, circuits designed at the logic level to satisfy timing constraints had difficulty satisfying those constraints after final layout. Obviously, failing to achieve design closure generates unacceptable time-to-market delays and costs. Today's proposed solution is to merge layout and logic synthesis, at least in terms of gate sizing, into one single optimization loop.

嵌入式系统设计正朝着越来越富于软件的解决方案发展。这引起了人们对硬件-软件协同设计的浓厚兴趣，它是一种通过并行硬件和软件开发以及减少集成时间来加快设计周期的方法。硬件-软件协同综合还意味着使用高级功能模型来获得详细、优化的软件和硬件实现。请注意这里综合和编译之间的区别：当我使用原始设计的数学表示时，我说的是综合，其中包含对特定实现风格的有限偏差。编译意味着从编程语言到汇编或机器代码的转换。在这种情况下，数学抽象是相同的。

Embedded system design is moving toward increasingly software-rich solutions. This creates a strong interest in hardware-software codesign as a means to speed up the design cycle by parallelizing hardware and software development, and by reducing integration time. Hardware-software cosynthesis also means using a high-level functional model to derive detailed, optimized software and hardware implementations. Note the difference between synthesis and compilation here: I say synthesis when I use a mathematical representation of the original design that contains limited bias toward a particular implementation style. Compilation implies the translation from a programming language to assembly or machine code. In this case, the mathematical abstraction is the same.

从这个角度思考，我惊讶地发现，早在 1967 年，DAC 就发表了关于软件设计的论文。那么，我们要回到未来了吗？基本区别在于感兴趣的软件类型。一开始，DAC 软件论文涵盖的活动范围从建筑到结构，从电子电路到“标准”软件（数据库和航空预订软件）。现在的重点主要是嵌入式软件。

Thinking in this context, I was surprised to see that as early as 1967, DAC presented papers on software design. Are we going back to the future, then? The basic difference is in the type of software that was of interest. In the beginning, DAC software papers spanned activities from buildings to structures, from electronic circuits to “standard” software (database and airline reservation software). Now the focus is mostly on embedded software.