抽象的:

Abstract:

设计自动化会议 40 周年,主题演讲旨在全面回顾这些年来 DAC 上展示的最相关研究成果,并确定电子设计自动化 (EDA) 未来的趋势和挑战。EDA 是一个独特而美妙的领域,多年来,研究、创新和商业一直在这里融为一体,过去 40 年取得的成就就是明证。
发表于: IEEE 计算机设计与测试 第 20 卷 第 6 期 ,2003 年 11 月 -12 月
页数: 59 - 75
出版日期: 2003年11月17日

ISSN信息:

ISSN Information:

出版商: IEEE

Alberto 在第 40 届设计自动化大会上发表主题演讲,并以此为基础撰写了这篇文章。在那次演讲中,他提出了一项大胆的电子设计自动化计划,即 EDATech,该计划将推动整个行业的发展,就像 SEMATECH 推动半导体制造业发展一样。

Alberto bases this article on remarks from his invited keynote speech at the 40th Design Automation Conference. In that speech, he proposed a bold initiative in electronic design automation, EDATech, which would drive the industry much like SEMATECH propelled semiconductor manufacturing.

— Rajesh Gupta,主编

—Rajesh Gupta, Editor in Chief

■ 非常荣幸能以主题演讲来庆祝设计自动化会议 40 周年,该演讲旨在全面回顾这些年来在 DAC 上提出的最相关的研究成果,并确定电子设计自动化 (EDA) 未来的趋势和挑战。浏览 DAC 会议记录并寻找相关论文确实是一项艰巨的任务。在此过程中,我希望找到我们 EDA 人员可以用来了解我们领域的历史及其命运的规律。

■ It Was A Great Honorto celebrate the 40th anniversary of the Design Automation Conference with a keynote lecture intended to place in perspective the most relevant research results presented at DAC in all these years and to identify trends and challenges for the future of electronic design automation (EDA). Going through the DAC proceedings, hunting for relevant papers, was indeed a formidable task. While doing so, I wanted to find regular patterns that those of us in EDA could use to understand the history of our field and its destiny.

在回顾我曾经是意大利古典学院的学生的背景时,我意外地得到了同胞的帮助:乔凡·巴蒂斯塔·维科,他是第一位从哲学角度分析历史及其模式的哲学家。他于 1650 年撰写了他的杰作《新科学》。维科的根本贡献是历史以规则的螺旋状模式重复自身(“corsi e ricorsi storici”)。

Fishing into my background as a former student of an Italian classical Lyceum, I found unexpected help from a fellow countryman: Giovan Battista Vico, the first philosopher who analyzed history and its patterns from a philosophical point of view. He wrote his masterpiece, Scientia Nova, in 1650. Vico's fundamental contribution was that history repeats itself with a regular spiral-like pattern (“corsi e ricorsi storici”).

维科将人类历史划分为三个阶段:神灵时代、英雄时代和人类时代。神灵时代的特点是人们通过感官获得知识。在这方面,事件和自然现象(大部分)是无法解释的,并归因于“外部”实体,例如古代神灵。

Vico identified three phases in mankind's history: the age of gods, the age of heroes, and the age of men. The age of gods is characterized by knowledge that comes to people from the use of their senses. In this respect, events and natural phenomena are inexplicable (for the most part) and attributed to “external” entities, like the ancient gods.

英雄时代的特点是人们利用想象力超越感官信息,找到对现实的最初抽象解释。这是创造力的时代,是人类伟大成就的基础。

The age of heroes is characterized by the use of imagination that lets people supersede the sensory information to find the first abstract interpretations of reality. It is the age of creativity, the foundation of great human achievements.

接下来的时期是人类时代,其特点是理性——理性分析剖析事件,在此期间,人们害怕新奇和创造力,因为没有分析可以保证任何倡议的成功,所以他们会陷入黑暗。维科认为人类时代是社会衰落的开始。然而,他发现,在经历了这一时期的颓废之后,人类将再次经历这三个阶段,回到下一个神时代。

The following period, the age of men, is characterized by reason—rational analysis that dissects events, during which people fear novelty and creativity as jumps into the dark because no analysis can guarantee any initiative's success. Vico identified the age of men as the beginning of decay in society. Yet he found that after the decadence of this period, mankind would again loop through the three stages, returning to the next age of gods.

EDA 时代

Ages of EDA

令人惊讶的是,我发现我可以在 EDA 的历史中发现类似的模式。为了确定 EDA 的年龄跨度,我使用了 DAC 的出勤数据,如图 1 所示。

Quite surprisingly, I found that I could identify similar patterns in the history of EDA. To determine the time span of the ages of EDA, I used attendance data from DAC, shown in Figure 1.

图 1.

1964 年至 2003 年 DAC 出席情况。

DAC attendance from 1964 to 2003.

在该图中,我们看到了最初的时期,即 1964 年至 1978 年,当时的出席率相当低。接下来是繁荣时期,即 1979 年至 1992 年,当时的出席率急剧上升。最后,从 1993 年到今天,相对停滞,并且在过去几年中明显下降。将这三个时期与维科所概括的神、英雄和人的时代联系起来似乎很自然!

In this diagram, we see an initial period, from 1964 to 1978, where attendance was fairly low. Next comes a period—from 1979 to 1992—of great prosperity with a very sharp increase in participation. Finally, from 1993 to today, there is relative stagnation and a marked decrease in the last few years. It seems natural to associate these three periods with the ages of gods, heroes, and men as outlined by Vico!

另一组有趣的统计数据与论文提交及其来源有关,如图 2 所示。

Another interesting set of statistical data relates to paper submissions and their origin, as shown in Figure 2.

图 2.

DAC 论文统计数据。

DAC paper statistics.

在该图中,神时代对应着行业论文的盛行;英雄时代对应着学术论文的明显增加;而男人时代则对应着学术论文的主导地位。

In this diagram, the age of gods corresponds to a prevalence of industry papers; the age of heroes, to a marked increase in academic papers; and the age of men, to a predominance of academic papers.

众神时代(1964 年至 1978 年)

Age of Gods (1964 to 1978)

在这一时期,行业先驱奠定了 EDA 的基础。在浏览最初几年的论文集时,我发现了一些具有开创性的论文,这些论文至今仍具有强大的影响力。我按相关主题对它们进行了分类,并将基础贡献分为五个领域:电路模拟;逻辑模拟和测试;MOS 时序模拟;线路布线;以及规则阵列。

In this period, industry pioneers laid the foundations of EDA. While browsing through the first few years' proceedings, I found seminal papers that continue to have a strong impact today. I classified them by relevant topics, and I clustered fundamental contributions into five areas: circuit simulation; logic simulation and testing; MOS timing simulation; wire routing; and regular arrays.

电路仿真

Circuit Simulation

电路模拟一直是重要的 DAC 主题,特别是与 IC 设计相关的主题。电路模拟在 IC 设计中的巨大成功一直是 EDA 行业诞生的主要推动力。IBM 研究人员是这些年来最突出的力量:Frank Branin 是确定电路模拟架构的先驱。在我看来,Brayton、Hachtel 和位于约克镇的 IBM TJ Watson 研究中心的同事为这一领域做出了根本性的革命性贡献:他们引入了我们今天所知的电路模拟背后的算法,从稀疏矩阵到后向微分公式。他们促成了两个重要程序的开发:IBM 的 Astap(高级统计分析程序)和加州大学伯克利分校的 Spice(集成电路重点模拟程序)。Ron Rohrer 和 Don Pederson 的早期贡献对于使这些程序成为多年来电路模拟的主力至关重要。

Circuit simulation has been an important DAC topic, especially as it relates to IC design. The great success of circuit simulation in IC designs has been a dominant driver in the birth of EDA as an industry. IBM researchers were the most prominent force in these years: Frank Branin was a pioneer in determining the architecture for circuit simulation. In my opinion, Brayton, Hachtel, and colleagues at IBM T.J. Watson Research Center in Yorktown made fundamental, revolutionary contributions to this field: They introduced the algorithms behind circuit simulation as we know it today, from sparse matrices to backward differentiation formulas. They enabled the development of two important programs: IBM's Astap (advanced statistical analysis program) and UC Berkeley's Spice (simulation program for integrated circuits emphasis). The early contributions of Ron Rohrer and Don Pederson were essential to making these programs the workhorses of circuit simulation for years and years.

逻辑仿真与测试

Logic Simulation and Testing

当 DAC 开始时,逻辑模拟已经投入使用一段时间了。IBM 和 CDC 等计算机公司依靠这项技术来调试他们的逻辑设计。对该领域的贡献不计其数,该领域的创始人在开发自动测试模式生成和故障模拟方面也发挥了重要作用。密歇根大学的 Ulrich 和 Hayes、南加州大学的 Breuer 和德克萨斯大学奥斯汀分校的 Szygenda 等人发挥了不可估量的作用。Tom Williams 及其同事发明了一种电平敏感扫描设计方法,IBM 的 Paul Roth 随后开发了 D 算法,改变了该行业设计计算机硬件和生成测试模式的方式。

Logic simulation had already been in use for some time when DAC started. Computer companies, such as IBM and CDC, relied on this technology to debug their logic designs. The contributions to this field are countless, and the field's founders also had a fundamental role in developing automatic test pattern generation and fault simulation. The role of Ulrich and Hayes at the University of Michigan; Breuer at the University of Southern California; and Szygenda at the University of Texas at Austin, to name a few, was invaluable. The invention of a methodology for level-sensitive scan design by Tom Williams and colleagues, and the consequent development of the D-algorithm by Paul Roth of IBM, changed the way in which this industry designed computer hardware and generated test patterns.

MOS 时序仿真

MOS Timing Simulation

利用 MOS 晶体管的准单向特性来加速电路仿真,最早出现在 1975 年 Gummel 和贝尔实验室同事的工作中。Gummel 的直觉是使用基于快速松弛的启发式算法来近似描述电路的常微分方程的解。他的洞察力是认识到,在分析数字电路的时序时,只要开关事件能够及时正确放置,其准确的波形并不重要。这一洞察力仍然是当今快速电路仿真的基础。

Exploiting the quasi-unidi-rectional characteristic of a MOS transistor to speed up circuit simulation first appeared in the work of Gummel and colleagues of Bell Labs in 1975. Gummel's intuition was to approximate the solution of the ordinary differential equations describing the circuits with a fast relaxation-based heuristic algorithm. His insight was to recognize that when analyzing a digital circuit's timing, its accurate waveforms are unimportant as long as the switching events could be correctly placed in time. This insight is still the basis of today's fast circuit simulation.

线路布线

Wire Routing

我们今天在工具中使用的大多数技术都是基于这一时期获得的结果。著名的 Lee 迷宫路由器于 1961 年(第一个 DAC 之前)开发,仍然是当今大多数路由器的基础。Hightower 线路扩展算法可以追溯到 1969 年,而通道路由的想法则来自 Hashimoto 和 Stevens 在 1971 年的工作。

Most of the techniques that we use today in our tools are based on the results obtained in this period. The famous Lee maze router developed in 1961 (before the first DAC), is still the basis for most of the routers in use today. The Hightower line extension algorithm dates back to 1969, and the idea of channel routing came from the work by Hashimoto and Stevens in 1971.

常规数组

Regular Arrays

随着大规模集成电路的出现,规则布局模式对于缩短设计时间的吸引力越来越大。研究人员开发了门阵列(在 IBM 称为主切片)和标准单元(在 IBM 称为主图像)作为自定义布局的替代方案。在此期间,IBM 和贝尔实验室广泛使用了集成工具,这些工具使用这些设计样式来自动布局电路。我记得这个想法的开始,当时一个门阵列集成电路有四个门,斯伦贝谢的一位研究人员讨论了使用自动化工具来优化电路的利用率。看看我们从那时起走过的路程:40 年来,单个芯片上的门数从 4 亿个增加到 4 亿个。

With the advent of large-scale ICs, the appeal of regular layout patterns for reducing design time was strong. Researchers developed gate arrays (called master slices at IBM) and standard cells (master images at IBM) as alternatives to custom layouts. In this period, IBM and Bell Labs made extensive use of integrated tools using these design styles for the automatic layout of circuits. I remember the beginning of this idea, when a gate array IC had four gates and a Schlumberger researcher discussed the use of automated tools to optimize the circuit's utilization. Look at the distance we've covered since then: in 40 years, from four to 400 million gates on a single chip.

商业方面

Business Side

观察家们认为计算机辅助设计对系统行业,尤其​​是计算机行业具有战略价值。IBM 和其他大公司认为它非常重要,值得投入大量资金和资源。内部 CAD 小组是强大的工程组织。在 DAC 会议记录中,我还注意到日本计算机和通信系统行业的强大影响力。这些贡献者撰写的论文描述了使用工具进行系统设计的统一方法,从而展示了 CAD 技术在全球范围内的战略价值。

Observers considered computer-aided design to be of strategic value to the system industry, and in particular, to the computer industry. IBM and the other large companies considered it important enough to warrant a sizable investment in funding and resources. Internal CAD groups were powerful engineering organizations. Looking at the DAC proceedings, I also noticed the strong presence of the Japanese computer and communication system industry. These contributors wrote papers describing unified approaches to system design using tools, thus showing the strategic value of CAD technology worldwide.

在此期间,企业家们创立了第一代 CAD 公司:1969 年成立的 Applicon、1970 年成立的 Calma 和 1972 年成立的 Computervision。它们都支持几乎相同的设计活动:在定制工作站上编辑艺术品。它们的业务模式专注于工作站销售;它们将软件视为附加组件。这些第一代 CAD 公司如今已无一幸存。我可以找出它们倒闭的几个原因:

During this period, entrepreneurs founded the first-generation CAD companies: Applicon in 1969, Calma in 1970, and Computervision in 1972. They all supported pretty much the same design activity: artwork editing on customized workstations. Their business models focused on workstation sales; they considered the software as an add-on. Of these first-generation CAD companies, none is alive today. I can identify several causes for their demise:

  • 他们的产品架构由定制硬件和复杂软件组成,这些软件大多用汇编代码编写。由于设计新型工作站需要巨额投资,他们很难跟上技术进步的步伐。严重的软件移植问题和有限的销售量进一步加剧了这一问题,难以支撑投资。

  • The architectures of their products consisted of customized hardware with complex software written mostly in assembly code. It was difficult for them to keep abreast of technology advances because of the huge investments needed to design novel workstations. This problem was further aggravated by severe software porting problems and a limited sales volume to support the investments.

  • 他们的产品忠诚度有限,因为客户认为其附加值较低。

  • Their products had limited loyalty because customers perceived their value added as low.

  • 这些公司对于市场变化和客户需求的了解有限。

  • These companies had a limited understanding of market evolutions and customer needs.

这些因素导致完全缺乏创新并最终过时。

These factors contributed to a complete lack of innovation and eventual obsolescence.

在结束“众神时代”之前,我必须提到 Pat Pistilli 的特殊作用:他让 DAC 从少数几个与会者发展到超过 5,000 名技术会议参与者。我们庆祝 DAC 成立 40 周年,就是对他远见卓识的致敬。

I cannot conclude the age of gods without mentioning Pat Pistilli's particular role: He nurtured DAC from a handful of attendees to over 5,000 at the technical sessions. Our celebration of DAC's 40th anniversary is a tribute to his vision.

英雄时代(1979年至1993年)

Age of Heroes (1979 to 1993)

令人惊讶的是,在 1979 年至 1993 年间,EDA 领域的各个方面都出现了爆炸式增长。在此期间参加 DAC 是一种非常难忘的经历。演示室和展品中洋溢着活力和热情,这是社区健康发展的明显标志。DAC 成为 EDA 各个方面许多重要贡献的来源,从物理验证到布局综合,从逻辑综合到形式验证,从系统级设计到硬件加速。技术社区扩展到非线性和组合优化、控制、人工智能和逻辑等专业领域。在寻求新方法和新工具的过程中,社区还探索了未能产生预期结果的途径。有几年,使用专家系统和神经网络的论文占据了会议的主导地位;许多小组讨论了这些方法的潜在影响。然而今天,它们的影响已经所剩无几,我很高兴地报告,DAC 在 2003 年没有在这些领域发表任何论文!

It is surprising to see that between 1979 and 1993 the EDA field exploded in all its aspects. To be at DAC during this period was quite an experience. The vibrancy and enthusiasm that permeated the presentation rooms and the exhibits was a clear sign of the community's healthy growth. DAC became the source of many essential contributions in all aspects of EDA from physical verification to layout synthesis, from logic synthesis to formal verification, and from system-level design to hardware acceleration. The technical community expanded to reach areas of expertise in nonlinear and combinatorial optimization, control, artificial intelligence, and logic. In this quest for new methods and tools, the community also explored avenues that did not yield the promised results. There were years when papers using expert systems and neural networks dominated the conference; many panels discussed the potential impact of these methods. Yet today, little is left to show of their impact, and I am glad to report that DAC presented no papers in these areas in 2003!

在这些年里,企业家们创立了最成功的 EDA 公司。最杰出的研究小组聘请了数名 EDA 博士;行业对学生进入这一领域施加了巨大压力。这个年龄段的主要贡献集中在几个不同的主题上。

During these years, entrepreneurs founded the most successful EDA companies. The most prominent research groups hired several PhDs in EDA; industry exerted a strong pressure on students to enter this area. The main contributions from this age cluster into several distinct topics.

验证和测试

Verification and Testing

这一领域包括两条主要工作路线。一条侧重于使电路仿真比 Spice 快几个数量级;另一条侧重于形式化技术,以证明电路能够正确运行。在第一个领域,Richard Newton、Albert Ruehli 和我等人在 1980 年左右对基于松弛的技术和混合模式仿真的研究为当今使用的快速 MOS 模拟器奠定了基础。Bryant 的其他工作侧重于数字电路的仿真,其速度比 Spice 快两个数量级,精度介于电路仿真和逻辑仿真之间。

This field encompassed two main lines of work. One focused on making circuit simulation orders of magnitude faster than with Spice; the other focused on formal techniques to prove that the circuit would perform correctly. In the first domain, the work on relaxation-based techniques and mixed-mode simulation by, among others, Richard Newton, Albert Ruehli, and myself around 1980, established the basis for the fast MOS simulators in use today. Other work by Bryant focused on the simulation of digital circuits with a two-order-of-magnitude speedup over Spice and accuracy between the one offered by circuit simulation and the one offered by logic simulation.

随着几何尺寸的缩小,互连的影响越来越大。1981 年,Penfield 和 Rubinstein 提出的互连延迟模型得到了广泛应用。卡内基梅隆大学的 Pileggi 和 Rohrer 着手解决互连模拟问题,并于 1988 年开发了渐近波形评估 (AWE) 方面的成果。

Interconnects had an increasing impact as geometries scaled down. The interconnect delay model introduced by Penfield and Rubinstein in 1981 saw extensive use. Pileggi and Rohrer at CMU tackled interconnect simulation, developing their results on asymptotic waveform evaluation (AWE) in 1988.

形式化技术最初旨在回答两个不同的门网络是否计算相同的布尔函数的问题。形式化验证的首次使用还是在 IBM 的 Bahnsen 时代,但这项工作从未出现在 DAC 论文集中。1986 年,Bryant 在二元决策图 (BDD) 方面的开创性工作通过引入布尔函数的规范形式和非常快速的操作算法彻底改变了该领域。Coudert 和 Madre 使用 BDD 进行有限状态机等价性的工作,以及 Ed Clarke、Ken McMillan、Dave Dill 和 Bob Kurshan 在 20 世纪 90 年代初进行模型检查的工作,将形式化验证提升到了更高的抽象层次。模型检查解决了验证由 FSM 表示的顺序系统是否满足描述为状态和转换上定义的逻辑命题的属性或另一个 FSM 的问题。

Formal techniques first aimed at answering the question of whether two different networks of gates computed the same Boolean function. The first use of formal verification was again at IBM by Bahnsen during the age of gods, but this work never appeared in the DAC proceedings. The seminal work by Bryant on binary decision diagrams (BDDs) in 1986 revolutionized the field by introducing a canonical form for Boolean functions and very fast manipulation algorithms. The work by Coudert and Madre on finite-state machine equivalence using BDDs, and the work by Ed Clarke, Ken McMillan, Dave Dill, and Bob Kurshan on model checking in the early 1990s, elevated formal verification to higher levels of abstraction. Model checking tackled the problem of verifying whether a sequential system represented by an FSM would satisfy a property described as a logic proposition defined on the states and transitions, or as another FSM.

在测试领域,著名的基于D算法的Podem-X计划于1981年在Prabhu Goel的指导下在IBM诞生。

In the testing area, the famous Podem-X program based on the D-algorithm emerged at IBM under the direction of Prabhu Goel in 1981.

布局

Layout

在表示和基本操作层面,艺术品编辑发生了根本性的变化。在前一个时期,设计师对每个设计步骤使用不同的数据存储库,并执行从一种数据格式到另一种数据格式的繁琐转换工作。20 世纪 80 年代初,牛顿在加州大学伯克利分校使用 Squid、Oct 和 VEM 的工作;以及奥斯特豪特使用 Magic 的工作,通过展示拥有统一数据库和图形用户界面的可能性,彻底改变了该领域。这项工作的影响不容小觑。OpenAccess 数据库借鉴了牛顿的开创性工作;一些高级物理设计的数据表示基于奥斯特豪特提出的角拼接思想。

At the representation and basic manipulation level, artwork editing saw a fundamental change. In the previous period, designers used different data repositories for each of the design steps and performed tedious translation work from one data format to another. In the early 1980s, Newton's work at UC Berkeley with Squid, Oct, and VEM; and Ousterhout's work with Magic revolutionized the field by showing that it was possible to have a unified database and graphical user interface. I cannot overemphasize the impact of this work. The OpenAccess database has borrowed from Newton's seminal work; some of the data representations for advanced physical design are based on the idea of corner stitching introduced by Ousterhout.

另一个革命性的想法源自硅片编译和布局语言的研究。几个研究小组大约在同一时间探索了这一领域。这些小组分别来自麻省理工学院 (Battali)、加州理工学院 (Mead 的团队和 Bristle Block 硅片编译器) 和贝尔实验室 (Gummel;Buric 及其同事和 L 布局语言)。这个想法是将计算机科学文化的某些部分注入 IC 设计中。尽管这种方法在智力上很优雅且功能强大,但目前的工具中几乎没有保留它。

Another revolutionary idea arose from work on silicon compilation and layout languages. Several research groups explored this area at around the same time. These groups were at MIT (Battali), Caltech (Mead's group with the Bristle Block silicon compiler), and Bell Labs (Gummel; Buric and colleagues with the L layout language). The idea was to inject IC design with some parts of the computer science culture. Although the approach was intellectually elegant and powerful, little of it remains in present tools.

两位物理学家 Kirkpatrick 和 Gelatt 利用他们的物理知识开发了模拟退火算法,并于 1980 年在 IBM 引入该算法来解决门阵列布局的布局问题。这种方法一经公布,便引发了大量关于其有效实施和理论特性的研究。该算法针对标准单元和宏单元布局以及全局布线进行了定制。从英特尔到 DEC,从摩托罗拉到 TI,大多数大公司都使用了加州大学伯克利分校 Sechen 编写的 TimberWolf 系统。

Two physicists, Kirkpatrick and Gelatt, used their knowledge of physics to develop simulated annealing, introducing it at IBM in 1980 to solve a placement problem for gate array layout. Once publicized, this approach gave rise to a great deal of research on its efficient implementation and theoretical properties. Customizations of the algorithm took place for standardcell and macrocell layout as well as for global routing. Most of the major companies, from Intel to DEC, and from Motorola to TI, used the TimberWolf system written by Sechen at UC Berkeley.

这些年,理论计算机科学家也对研究布局设计的组合方面产生了浓厚的兴趣。Rivest 和 Pinter(麻省理工学院)在布线方面的工作,以及 Karp(加州大学伯克利分校)在布局和布线方面的工作就是这种参与的典型例子。这清楚地表明 EDA 成功地吸引了其他社区的参与。在此期间,加州大学伯克利分校的 Kuh 的工作产生了用于宏单元设计的集成布局系统和用于布局和布线的点工具;这些系统对该领域产生了巨大影响。

These years also witnessed significant interest from theoretical computer scientists about studying the combinatorial aspects of layout design. The work of Rivest and Pinter (MIT) on routing, and of Karp (UC Berkeley) on placement and routing, were examples of this involvement. This was a clear sign of EDA's success in attracting other communities to contribute. During this time, the work of Kuh at UC Berkeley yielded integrated layout systems for macrocell design and point tools for placement and routing; these systems had a great impact on the field.

逻辑综合

Logic Synthesis

1979 年,Darringer、Joyner 和 Trevillyan 发表了一篇开创性的论文,介绍了逻辑综合。这些研究人员使用基于窥孔规则的优化来生成设计的高效门级表示。紧接着这项工作,IBM 于 1979 年独立地开始了另一种布尔优化方法。Brayton 和 Hachtel 与加州大学伯克利分校的 Newton 和我合作开发了两级逻辑优化器 Espresso 和两个多级逻辑优化器,即 Yorktown Silicon Compiler 和多级交互式综合 (MIS) 系统。这项工作得到了国防高级研究计划局 (DARPA) 的支持,历时 10 多年。在 MIS 的早期开发中,它包含一个技术独立的阶段,用于操纵和优化布尔函数,然后是技术映射步骤,将优化的布尔函数映射到门库。所有大公司(英特尔、ST、TI、摩托罗拉、霍尼韦尔、DEC 和飞利浦)很快都采用了该版本的 MIS。

A seminal paper by Darringer, Joyner, and Trevillyan introduced logic synthesis in 1979. These researchers used peephole rule-based optimization to generate efficient gate-level representations of a design. Immediately following this work and somewhat independently, another approach to Boolean optimization began at IBM in 1979. Brayton and Hachtel, in collaboration with Newton and me at UC Berkeley, developed the two-level logic optimizer Espresso, and two multilevel logic optimizers, the Yorktown Silicon Compiler and the Multilevel Interactive Synthesis (MIS) system. This work, supported by the Defense Advanced Research Projects Agency (DARPA), spanned more than 10 years. In MIS’ early development, it incorporated a technology-independent phase that manipulated and optimized Boolean functions, followed by a technology-mapping step that mapped the optimized Boolean functions to a library of gates. All the major companies—Intel, ST, TI, Motorola, Honeywell, DEC, and Philips—soon adopted this version of MIS.

在第二阶段,常见的方法是使用基于规则的技术,例如通用电气的 Aart DeGeus 及其同事开发的 Socrates 系统中的技术。Kurt Keutzer 后来展示了如何使用 Aho 和 Ullman 的编译器工作来获得高效的技术映射器。这个想法是将技术映射表述为一个树覆盖问题,并用动态规划来解决。这个想法在当今的大多数逻辑综合系统中仍然适用。日本富士通、NTT 和 NEC 的工作非常出色,他们主要基于 IBM 的 Darringer 的原创工作来制作有效的逻辑综合系统。

In the second phase, the common approach was to use rule-based techniques like those in the Socrates system, developed at General Electric by Aart DeGeus and colleagues. Kurt Keutzer later showed how to use the compiler work by Aho and Ullman to obtain a highly efficient technology mapper. The idea was to formulate technology mapping as a tree-covering problem to be solved with dynamic programming. This idea still finds a home in most of today's logic synthesis systems. The work in Japan at Fujitsu, NTT, and NEC was outstanding in producing working logic synthesis systems based primarily on the original work of Darringer at IBM.

逻辑综合是我们社区的一大成就,因此,它是许多论文的来源,并引起了其他相关领域的极大兴趣。在 1985 年国际测试大会的主题演讲中,我断言测试模式生成和逻辑综合确实是同一枚硬币的两个面。Keutzer、Devadas、Malik、McGeer 和 Saldanha 与 Brayton、Newton 和我合作完成的工作展示了使用逻辑综合技术进行冗余消除和延迟测试的几个结果。V. Agrawal、Tim Cheng 等人的新测试算法源于这两个领域的交叉融合。

Logic synthesis was a great achievement of our community, and as such, it was the source of many papers and attracted significant interest from those in other connected fields. In a keynote address at the International Test Conference in 1985, I asserted that test pattern generation and logic synthesis were indeed two faces of the same coin. The work by Keutzer, Devadas, Malik, McGeer, and Saldanha in collaboration with Brayton, Newton, and me demonstrated several results in redundancy removal and delay testing using logic synthesis techniques. New testing algorithms from V. Agrawal, Tim Cheng, and others arose from the cross-pollination of the two fields.

在逻辑综合的成熟时期,Coudert 和 Madre 能够通过使用 BDD 显著加速基于布尔函数的合取范式 (CNF) 表示的逻辑综合算法。

In the mature period of logic synthesis, Coudert and Madre were able to considerably accelerate logic synthesis algorithms based on conjunctive normal form (CNF) representations of Boolean functions by using BDDs.

硬件描述语言

Hardware Description Languages

逻辑综合这一技术工作更适合归类为逻辑优化,因为算法将数字电路的布尔表示转换为优化的等效表示。综合意味着在两个抽象层之间架起一座桥梁。硬件描述语言的诞生是为了比布尔函数更高效、更紧凑地表示数字电路。真正的综合工作是将 HDL 描述映射到门网络表中。不幸的是,HDL 的开发与逻辑优化工作无关。这意味着逻辑综合算法无法处理 HDL 的所有构造,例如 Verilog(由 Moorby 及其同事提出)和 VHDL。因此,有必要将这些语言的使用限制在其所谓的可综合子集内。尽管 HDL 在设计周期早期引入验证以缩短设计时间方面确实取得了很大进步,但子集化的需求表明 HDL 在语义方面存在问题。

The technical work characterized as logic synthesis would be better classified as logic optimization because the algorithms change a digital circuit's Boolean representation into an optimized equivalent representation. Synthesis implies a bridge between two layers of abstractions. Hardware description languages were born to more efficiently and compactly represent digital circuits than Boolean functions. The real synthesis job became mapping an HDL description into a netlist of gates. Unfortunately, HDL development began independently of the work on logic optimization. This implied that logic synthesis algorithms could not tackle all the constructs of HDLs such as Verilog (proposed by Moorby and colleagues) and VHDL. It thus became necessary to restrict the use of these languages to their so-called synthesizable subset. Although HDLs were indeed a great advance in terms of introducing verification early in the design cycle to reduce design time, the need for subsetting showed that HDLs had problems on the semantic side.

这些年来,HDL 之争非常有趣:Verilog 是一种专有语言(Gateway Design 销售 Verilog 模拟器并授权该语言),而 VHDL 是 DARPA 在 VHSIC 计划中支持的开放标准。我们这些从业者在 DAC 上就一种语言比另一种语言更优越进行了无数次辩论。当 Verilog 公开时,两者之间主要存在外观上的差异,尽管大多数人根据个人喜好表达了对其中一种或另一种的强烈喜爱。Joe Costello 非常雄辩地指出,为一项任务采用两种标准通常是一个坏主意:“……采用 VHDL 是设计自动化历史上最大的错误之一,导致用户和 EDA 供应商浪费了数亿美元……”

The HDL battle was very interesting during these years: Verilog was a proprietary language (Gateway Design was selling a Verilog simulator and licensed the language) while VHDL was an open standard supported by the DARPA within the VHSIC program. We practitioners had countless debates about the superiority of one language over the other at DAC. When Verilog became public, there were mostly cosmetic differences between the two, even though most people expressed a strong attachment to one or the other, according to their personal taste. Joe Costello very eloquently argued that the adoption of two standards for a single task is in general a bad idea: “ … Adoption of VHDL was one of the biggest mistakes in the history of design automation, causing users and EDA vendors to waste hundreds of millions of dollars…”

硬件加速

Hardware Acceleration

所有 EDA 方法都需要大量的计算时间来对非常大的数据集执行复杂的算法。在技术大发展时期,定制硬件来加速 EDA 算法的执行非常有吸引力。像往常一样,IBM(我相信它是对该领域影响最大的唯一机构)提出了一种用于逻辑模拟的专用架构,即 Pfister 及其同事的 Yorktown 模拟引擎 (YSE)。性能上的巨大优势推动了强劲的行业活动;企业家们成立了几家新公司来服务硬件加速市场。硬件加速的理念扩展到其他 EDA 领域,包括线路布线(通过 IBM 的 Ravi Nair 及其同事)。然而,它在其他领域没有足够的吸引力来复制 YSE 的成功。

All EDA approaches require a massive amount of compute time to execute complex algorithms on very large data sets. In a great expansion period for the technology, customized hardware to speed up the execution of EDA algorithms was extremely appealing. As usual, IBM (which I believe is the single institution with the most impact on this field) proposed a special-purpose architecture for logic simulation, the Yorktown Simulation Engine (YSE), by Pfister and colleagues. The great advantages in performance drove strong industry activity; entrepreneurs formed several new companies to serve the hardware acceleration market. The idea of hardware acceleration extended to other EDA fields, including wire routing (via Ravi Nair and colleagues at IBM). However, it did not have enough appeal in other areas to repeat the success of YSE.

与此同时,研究人员还寻求另一种思路,即使用通用并行计算机来实现类似的性能优势,但开发成本更低。20 世纪 80 年代末,计算机设计界对并行架构表现出浓厚的兴趣。Thinking Machines 采用由麻省理工学院的 Danny Hillis 设计的大规模并行架构,在研究和工业界(包括 EDA)引起了轰动。这家围绕这台机器成立的公司传播了这种计算方法,并吸引了该领域一些最优秀的人才。例如,诺贝尔奖获得者 Richard Feynman 设计并实现了处理器间通信的路由算法;他在 Thinking Machines 的厂房里花了很多时间。关于算法和应用的即兴辩论很常见;当时最杰出的科学家举办了研讨会。研究人员为这种架构开发了算法,包括用于电路和逻辑模拟以及布局和布线的算法。然而,由于缺乏对最终用户需要完整解决方案而不是强大硬件的理解,这些机器的工业用途仅限于研究实验室;这种情况最终导致了公司的倒闭。

In parallel with this work, researchers pursued the alternative idea of using general-purpose parallel computers to achieve similar performance advantages but at a lower development cost. In the late 1980s, the computer design community showed significant interest in parallel architectures. Thinking Machines, using a massively parallel architecture designed by Danny Hillis at MIT, generated excitement in research and industrial communities, including EDA. The company formed around this machine disseminated this approach to computing and attracted some of the very best minds in the field. For example, Nobel laureate Richard Feynman designed and implemented the routing algorithms for the communication among processors; he spent many hours on Thinking Machines' premises. Impromptu debates about algorithms and applications were common; the most prominent scientists of the time gave seminars. Researchers developed algorithms for this architecture, including those for circuit and logic simulation, and for placement and routing. However, the lack of understanding that final users needed complete solutions, rather than powerful hardware, limited the industrial use of these machines to research laboratories; this situation eventually led to the demise of the company.

在同一时期,EDA 中的其他人积极追求并使用并行架构,例如 N-cube、Sequent 和 Intel 超立方体。然而,到目前为止,还没有人出售基于这些机器的商业工具。我相信,具有不同程度异构性的并行计算仍然是 EDA 和其他工程应用的重要结果尚未开发的来源。然而,在并行计算得到广泛使用之前,研究人员必须解决软件支持的基本问题。

During the same time period, others in EDA actively pursued and used parallel architectures such as the N-cube, Sequent, and Intel hypercube. Up to now, however, no one has sold a commercial tool based on these machines. I believe that parallel computing with various degrees of heterogeneity is still an untapped source of important results for EDA and other engineering applications. Before parallel computing is of widespread use, however, researchers must solve the fundamental problem of software support.

高层设计

High-Level Design

高级或系统级设计是通向未来的桥梁。我们都同意,提高抽象级别对于将设计效率提高几个数量级至关重要。我确实对这个领域充满热情,我相信我们的未来取决于该领域的设计方法和工具的成功。基础工作(由 Thomas、Parker 和 Gajski 完成)始于 20 世纪 80 年代的高级综合。这项工作几乎与逻辑综合同时开始,研究人员开发了几种商业工具。尽管如此,设计界尚未广泛接受这种方法;仍有许多工作要做。

High- or system-level design is a bridge to the future. We all agree that raising the level of abstraction is essential to increasing design productivity by orders of magnitude. I am indeed very passionate about this field, and I believe our future rides on the success of design methodologies and tools in this area. The foundational work (by Thomas, Parker and Gajski) started in the 1980s with high-level synthesis. This work started almost in parallel with logic synthesis, and researchers developed several commercial tools. Despite these facts, the design community has not widely accepted this approach; much work remains to be done.

基本问题是,是什么让逻辑综合成功,又是什么让高级综合的采用如此困难?我认为,高级综合的原始工作过于笼统;设计人员不得不探索太多替代方案,而工具很难在这场游戏中击败人类。然而,当系统级设计专注于受限架构(如 DSP 和基于微处理器的架构)时,高级综合在行业中取得了一定程度的成功。DeMan 和 Rabaey 在 IMEC Cathedral 系统上的工作就是这一较窄领域成功的一个例子。系统中嵌入的硬件-软件协同设计方法(如斯坦福大学的 Vulcan、Paulin 的 Flex、布伦瑞克大学的 Cosyma 和加州大学伯克利分校的 Polis)是其他例子。

The basic question is what made logic synthesis successful, and what made the adoption of high-level synthesis so difficult? I believe that the original work on high-level synthesis was too general; designers had to explore too many alternatives, and the tools had a difficult time beating humans at this game. However, when system-level design focuses on constrained architectures such as DSPs and those based on microprocessors, high-level synthesis has had a degree of success in industry. The IMEC work by DeMan and Rabaey on the Cathedral system is one example of success in this narrower domain. Hardware-software codesign approaches embedded in systems—such as Vulcan at Stanford, Flex by Paulin, Cosyma at Braunschweig University, and Polis at UC Berkeley—are other examples.

在此期间,Ed Lee 开发了 Ptolemy,Harel 开发了 Statecharts,用于在算法层面进行设计捕获和验证;这项工作影响了当今嵌入式系统设计的方法。在软件设计方面,INRIA 的 Berry 和 Benveniste 以及 Verimag 的 Caspi 及其同事提出了同步语言(Esterel、Signal 和 Lustre)。

During this period, Ed Lee developed Ptolemy and Harel developed Statecharts for design capture and verification at the algorithmic level; this work influences present approaches to embedded-system design. In software design, Berry and Benveniste at INRIA, and Caspi and colleagues at Verimag have proposed synchronous languages (Esterel, Signal, and Lustre).

EDA 研究与科学界的相关性

Relevance of EDA Research to the Scientific Community

在此期间,EDA 研究备受关注,在电气工程和计算机科学领域同样受到关注。这项工作的重要性在 EDA 研究人员获得的众多奖项以及以下惊人的统计数据中显而易见:根据 CiteSeer 数据库,被引用次数最多的三篇计算机科学论文来自 EDA。它们依次为:

During this period, EDA research was in the spotlight and equally pursued in electrical engineering and in computer science. The relevance of this work becomes apparent in the many awards that EDA researchers collected and by the following astonishing statistic: According to the CiteSeer database, the three most cited computer science papers come from EDA. They are, in order,

  • “通过模拟退火进行优化”,Kirkpatrick 等人,1983 年;

  • “Optimization by Simulated Annealing,” Kirkpatrick et al., 1983;

  • “基于图形的布尔函数操作”,Bryant,1986 年;

  • “Graph-Based Manipulation of Boolean Functions,” Bryant, 1986; and

  • “状态图:复杂系统的可视化形式”,Harel,1987年。

  • “Statecharts: a Visual Formalism for Complex Systems,” Harel, 1987.

你可能会说,这些数据并不能说明科学的卓越性,而是我们的社区在引用他人作品方面比其他更传统的计算机科学领域更慷慨。但无论如何,我认为频繁引用是一个积极的方面。

You could argue that this data does not show scientific excellence but rather that our community is more generous in quoting other people's work than other, moretraditional computer science areas. But I consider frequent citation a positive aspect, anyhow.

商业方面

Business Side

第二代和第三代 EDA 公司也在这一时期成立。第二代公司 Daisy、Mentor 和 Valid 成立于 1980 年至 1981 年,主要服务于数字设计市场,提供工作站上的原理图数据采集和仿真服务。Daisy 和 Valid 会自行构建工作站,这与第一代公司的传统做法一致。相比之下,Mentor 则通过原始设备制造商协议销售 Apollo 工作站。硬件销售是这三家公司收入的重要组成部分。

Second- and third-generation EDA companies formed during this period. Second-generation companies—Daisy, Mentor, and Valid—arose in the 1980 to 1981 time frame to serve the digital design market with schematic data capture and simulation on workstations. Daisy and Valid would build their own workstations, in line with the traditional approach of the first-generation companies. In contrast, Mentor sold Apollo workstations with an original equipment manufacturer agreement. Hardware sales were a substantial part of all three companies' revenues.

1982 年,企业家们成立了 SDA 和 ECAD,这两家公司于 1987 年合并成立了 Cadence。这两家公司是纯软件公司的首批典范。由于我参与了 SDA 的创立,所以我想分享一些你们可能不知道的小故事。ECAD 和 SDA 实际上从一开始就应该是一家公司,但 Paul Huang 已经完成了他的物理设计验证系统 Dracula,并希望在 SDA 方面准备就绪之前迅速上市。SDA 准备在 1987 年上市——这一天投资者至今仍称之为“黑色星期一”。此后几个季度,股市状况阻碍了任何 IPO。因此,Costello、Jim Solomon、Paul Huang 和 Glen Antle 认为最好的策略是通过与 ECAD 合并将 SDA 上市。他们将合资公司命名为 Cadence。

In 1982, entrepreneurs founded SDA and ECAD, which merged in 1987 to create Cadence. These companies were the first example of software-only companies. Because I was involved in SDA's creation, I would like to share a tidbit that many of you might not know. ECAD and SDA were actually supposed to be one company from the very beginning, but Paul Huang had already completed Dracula, his physical-design verification system, and wanted to go to market quickly, before SDA's side of the equation was ready. SDA prepared to go public in 1987—on the day that investors still call Black Monday. Stock market conditions prevented any IPOs for a few quarters afterward. Thus, Costello, Jim Solomon, Paul Huang, and Glen Antle felt that the best strategy was to make SDA public through its merger with ECAD. They called the joint company Cadence.

在此期间,其他人基于硅编译和符号布局的概念成立了 Silicon Compilers 和 Silicon Design Labs。ViewLogic 从 PC 的角度进军 EDA 市场,旨在为数字设计提供低成本解决方案。企业家们成立了 Gateway,将 Verilog 及其相关模拟器商业化。

During this period, others founded Silicon Compilers and Silicon Design Labs, based on the concepts of silicon compilation and symbolic layout. ViewLogic was pursuing the EDA market from the PC angle, aiming at low-cost solutions for digital design. Entrepreneurs formed Gateway to commercialize Verilog and its associated simulator.

1987 年,Optimal Solutions Inc. (OSI) 在北卡罗来纳州成立。没有多少人知道这是 Synopsys 的原名!到那时,很明显,考虑到利润率的差异,销售工作站硬件并不是一个有吸引力的商业模式。尽管这种共识正在形成,但直到 1990 年,EDA 社区的知名人士仍对“纯软件”公司的商业模式持负面态度,称他们不知道有哪家 EDA 公司不销售工作站硬件就能长期成功。专业硬件加速公司也在此期间成立:Quickturn、PiE Design 和 IKOS 等。如今,不再有独立的硬件加速公司;大多数公司已被并购所吸收。

In 1987, Optimal Solutions Inc. (OSI) was incorporated in North Carolina. Not many people know that this was the original name for Synopsys! By that time, it was clear that selling workstation hardware was not an appealing business model, given the difference in margins. Despite this developing consensus, as late as 1990, visible figures in the EDA community commented negatively on the business model of “software only” companies, saying that they knew of no long-term successful EDA company that did not sell workstation hardware. Specialized hardware acceleration companies also started during that period: Quickturn, PiE Design, and IKOS, among others. Today, there are no more independent hardware acceleration companies; mergers and acquisitions have absorbed most.

尽管 IC 和系统公司有很强的动机采用这些商业解决方案,但 EDA 的战略价值仍使内部投资保持较高水平。尤其是贝尔实验室和 IBM 在工具和环境方面领先于竞争对手。

Even though there was a strong incentive for IC and system companies to adopt these commercial solutions, the strategic value of EDA kept internal investment high. In particular, Bell Labs and IBM were pulling ahead of the competition in terms of tools and environments.

在接下来的几年里,由于通用工作站的主导地位,第二代商业模式(硬件加软件)被证明是不可持续的。Daisy 和 Valid 通过收购逐渐走向衰落,而 Mentor 则通过重塑自我来保持竞争力和经济可行性。Silicon Compilers 和 Silicon Design Labs 也在一系列并购中消失。硅编译的基本形式没有足够重视最终结果的性能和面积。此外,布局语言和符号布局系统在习惯于用图像和几何图形表示设计的社区中不被接受。

In the next few years, the second-generation business model—hardware plus software—proved unsustainable because of the dominance of general-purpose workstations. Daisy and Valid died a slow death through acquisition, while Mentor reinvented itself to sustain competitiveness and remain economically viable. Silicon Compilers and Silicon Design Labs also disappeared through a series of mergers and acquisitions. In its basic form, silicon compilation did not pay enough attention to the final result's performance and area. In addition, layout languages and symbolic layout systems did not find acceptance in a community used to representing designs with images and geometries.

男人时代(1993 年至 2002 年)

Age of Men (1993 to 2002)

在我看来,1993 年是我们社区新阶段的开始。技术创新开始放缓。从华尔街的角度来看,供应商社区已经成熟,导致更加关注底线,减少冒险。我引用我的同事兼朋友理查德·牛顿 1995 年 DAC 主题演讲:“如果今天我想在这里提出一点,那就是作为一门学科,无论是在行业还是在学术界,我们今天都没有承担足够的风险。”

In my opinion, 1993 was the beginning of a new phase in our community. Technical innovation began slowing down. The vendor community became mature from Wall Street's point of view, leading to more attention to the bottom line and less risk taking. I quote the 1995 DAC keynote address of my colleague and friend, Richard Newton: “If there is a single point I wish to make here today, it is that as a discipline, both in industry and in academia, we are just not taking enough risks today.”

这一时期恰逢网络及其应用的爆炸式增长。新兴的网络吸引了电气工程和计算机科学领域最优秀的人才和人才,同时也吸引了风险投资。这种情况自然导致 EDA 创新率较低。与此同时,半导体行业继续按照摩尔定律推动技术发展,增加了 EDA 面临的技术挑战。片上系统 (SoC) 成为现实。

This period coincides with the explosion of the Web and its applications. The emerging Web was commandeering the best energies and minds in electrical engineering and computer science; it was also capturing venture capital funding. This situation naturally yielded a lower rate of EDA innovation. At the same time, the semiconductor sector continued to drive technology along the lines of Moore's law, increasing the technical challenges to EDA. System on chip (SoC) became a reality.

SoC 对不同的人来说意味着很多东西。我发现在日本和韩国,SoC 意味着内存和微处理器的集成;在其他地方,任何使用大量晶体管的东西都可以称为 SoC。在我看来,SoC 是将不同的设计风格集成到一个连贯的整体中。跨学科方法对于解决电子技术进步带来的复杂问题是必不可少的。

SoC means many things to different people. I found that in Japan and Korea, SoC meant the integration of memory and microprocessors; elsewhere, anything that uses large numbers of transistors would qualify as SoC. In my opinion, SoC is about integrating different design styles into a coherent whole. Interdisciplinary approaches are necessary to solve the complex problems posed by advances in electronics.

相关贡献

Relevant Contributions

关于这一时期的根本贡献,目前尚无定论。根据这一时期的特征,我不想在这里表明立场,将各种研究方法标记为成功或失败(现在下结论还为时过早),而只是对一些重要主题进行评论。我将把确定关键贡献的任务留给 10 年后发表主题演讲的演讲者!

The jury is still out as to the fundamental contributions of this period. In line with this period's characterization, I do not wish to take a position here by labeling various research approaches as successes or failures (it is simply too early to tell), but simply comment on some important topics. I will leave the task of identifying key contributions to the speaker delivering the keynote 10 years from now!

随着几何尺寸向亚微米范围迈进,物理验证已引起广泛关注。自测试已成为解决测试设备成本上升和要求提高的唯一解决方案。研究人员研究了异步设计方法和相关的综合问题,将其作为解决功耗限制和线路延迟不可预测性引起的性能问题的潜在解决方案。有意突破极限的设计师仍在努力应对深亚微米范式变化,寻找其极限以及收益是否值得冒这个险。随着芯片功能越来越多,模拟设计已成为瓶颈。在 SoC 中,游戏的名称已成为寻找模拟和数字组件之间的最佳匹配,而不是优化模拟部分的性能。由于模拟电路依赖于许多二阶效应,模拟设计更像是一门艺术而不是一门科学。我认为我们必须将科学纳入其中,使这项活动可重复且比现在快得多。

Physical verification has attracted much attention as geometries march toward the submicron range. Self-test has emerged as the only solution to rising costs and requirements for test equipment. Researchers have studied asynchronous design methods and the associated synthesis problem as potential solutions to performance problems arising from power consumption constraints and the unpredictability of wire delays. Designers interested in pushing the envelope still grapple with the deep-submicron paradigm change, seeking its limits and whether the gains are worth the approach's risks. As chips incorporate increasing functionality, analog design has become the bottleneck. In SoCs, the name of the game has become finding the best matches between analog and digital components, rather than optimizing the analog part's performance to death. Because of an analog circuit's dependency on many second-order effects, analog design has been more of an art than a science. I believe we must bring science into the picture to make this activity repeatable and much faster than it is today.

当布线延迟成为芯片设计中的重要问题时,使逻辑综合和布局分层成为可能的关注点分离开始在实现设计收敛方面遇到问题。也就是说,在逻辑级设计的电路在满足时序约束后很难满足这些约束。显然,无法实现设计收敛会导致不可接受的上市时间延迟和成本。今天提出的解决方案是将布局和逻辑综合(至少在门尺寸方面)合并为一个单一的优化循环。

When wiring delays became relevant in chip design, the separation of concerns that enabled the layering of logic synthesis and layout began having problems achieving design closure. That is, circuits designed at the logic level to satisfy timing constraints had difficulty satisfying those constraints after final layout. Obviously, failing to achieve design closure generates unacceptable time-to-market delays and costs. Today's proposed solution is to merge layout and logic synthesis, at least in terms of gate sizing, into one single optimization loop.

嵌入式系统设计正朝着越来越富于软件的解决方案发展。这引起了人们对硬件-软件协同设计的浓厚兴趣,它是一种通过并行硬件和软件开发以及减少集成时间来加快设计周期的方法。硬件-软件协同综合还意味着使用高级功能模型来获得详细、优化的软件和硬件实现。请注意这里综合和编译之间的区别:当我使用原始设计的数学表示时,我说的是综合,其中包含对特定实现风格的有限偏差。编译意味着从编程语言到汇编或机器代码的转换。在这种情况下,数学抽象是相同的。

Embedded system design is moving toward increasingly software-rich solutions. This creates a strong interest in hardware-software codesign as a means to speed up the design cycle by parallelizing hardware and software development, and by reducing integration time. Hardware-software cosynthesis also means using a high-level functional model to derive detailed, optimized software and hardware implementations. Note the difference between synthesis and compilation here: I say synthesis when I use a mathematical representation of the original design that contains limited bias toward a particular implementation style. Compilation implies the translation from a programming language to assembly or machine code. In this case, the mathematical abstraction is the same.

从这个角度思考,我惊讶地发现,早在 1967 年,DAC 就发表了关于软件设计的论文。那么,我们要回到未来了吗?基本区别在于感兴趣的软件类型。一开始,DAC 软件论文涵盖的活动范围从建筑到结构,从电子电路到“标准”软件(数据库和航空预订软件)。现在的重点主要是嵌入式软件。

Thinking in this context, I was surprised to see that as early as 1967, DAC presented papers on software design. Are we going back to the future, then? The basic difference is in the type of software that was of interest. In the beginning, DAC software papers spanned activities from buildings to structures, from electronic circuits to “standard” software (database and airline reservation software). Now the focus is mostly on embedded software.

商业方面

Business Side

我已经提到过互联网和高科技金融狂热给 EDA 行业带来的压力。当时,我经常每天接到两个招聘人员的电话,他们迫切地询问是否有学生有兴趣在一家知名的 EDA 公司工作,因为供应商领域没有足够的人手来维持 EDA 的发展。知名供应商有 20% 的员工被不必要地解雇,他们被互联网和 EDA 初创公司抢走了。1999 年,EDA 行业大约有 80 家初创公司。在此期间,Avanti、Ambit、Magma、Monterey、Get-to-Chip、Verisity 和 Verplex 等公司开始尝试挑战主导者。然而,如果我们回顾互联网泡沫破灭后的几年,我们会看到不同的景象:很少有 IPO(如果有的话),收购是唯一的退出策略;这不是一个美好的画面。

I already alluded to the stress on the EDA industry created by the Internet and high-tech financial frenzy. At that time, I often received two calls a day from recruiters, asking desperately if I had students interested in working at one of the established EDA companies, because there were not enough people to keep EDA going in the vendor space. Established vendors had unwanted terminations in the range of 20% of their workforce, losing them to Internet and EDA startups. In 1999, there were about 80 startups in EDA. During this period, companies such as Avanti, Ambit, Magma, Monterey, Get-to-Chip, Verisity, and Verplex started, trying to challenge the dominant players. However, if we look at the years after the Internet bubble burst, we see a different landscape: very few IPOs—if any—and acquisitions as the only exit strategy; not a pretty picture.

EDA 的未来

The Future of EDA

2000 年至 2003 年对整个高科技行业来说都是极具挑战性的时期。如图 3 所示,整体市场状况至少可以说是低迷的;全球半导体研发支出正在减少,因此 EDA 公司的总可用市场也在萎缩(根据 EDAC 的数据,2002 年下降了 3%)。生存和繁荣是一项重大挑战。

The period from 2000 to 2003 has been very challenging to the high-tech industry at large. As shown in Figure 3, overall market conditions are gloomy to say the least; global semiconductor R&D spending is decreasing, and consequently the total available market for EDA companies is shrinking as well (a 3% decline in 2002, according to EDAC). Staying alive and prospering is a major challenge.

图 3.

市场状况。

Market conditions.

与此同时,我们必须创新并投资新技术。EDA 必须适应变化的业务条件和结构。我们正目睹客户与供应商关系的重大变化。随着半导体和系统公司合理化其在 EDA 技术上的投资,合作伙伴关系变得越来越重要;所有这些都是鉴于半导体技术发生了根本性变化,需要前所未有的投资规模,同时暴露出当前设计方法和工具的局限性。因此,许多公司推迟推出 90 纳米技术节点也就不足为奇了。由于非经常性工程 (NRE) 和掩模成本,ASIC 设计的拥有成本正在迅速增加。公司避免设计启动,而是选择使用标准解决方案并通过软件进行定制。如果我们推断数据,它只有一个信息:以 ASIC 为中心的传统 EDA 市场正在消失。我们需要重新思考整个设计过程。系统级设计问题现在主导着未来电子系统新平台的定义。这种趋势今天并不十分明显,但它将变得越来越重要,直到主导设计过程。

At the same time, we have to innovate and invest in new technology. EDA must adapt to a changed business condition and structure. We are witnessing a substantial change in the client-vendor relationship. Partnerships are increasingly important as semiconductor and system companies rationalize their investments in EDA technology; all of this in view of a fundamental change in semiconductor technology that requires investments of a size never seen before, while at the same time exposing the limitations of the present design methodology and tools. It is thus no wonder that many companies have delayed introducing their 90-nanometer technology node. The cost of ownership for ASIC design is increasing rapidly because of nonrecurring engineering (NRE) and mask costs. Companies avoid design starts, choosing instead to work with standard solutions and customization by software. If we extrapolate the data, it has only one message: The traditional EDA market, centered on ASICs, is evaporating. We need to re-think the entire design process. System-level design concerns are now dominating the definition of new platforms for future electronic systems. This trend is not very visible today, but it will become increasingly important until it dominates the design process.

EDA 社区别无选择,只能寻找其他应用领域。EDA 的主要客户半导体行业正在为其产品寻找继个人电脑和手机之后的下一个杀手级应用。

There is no other choice for the EDA community than to look for other areas of application. The semiconductor industry, EDA's main customer, is looking for the next killer applications for its products, after PCs and cell phones.

社会规模应用

Societal-Scale Applications

鉴于我所在的大学以参与社会问题而闻名,我坚信高科技行业的下一个驱动力将涉及社会的全球利益。人们正在形成一种共识,即电子产品尚未渗透到人们非常感兴趣的应用领域。这些潜在的应用是社会利益信息技术研究中心的重点,该中心是加州大学的一个非常广泛的项目,以伯克利为中心,由加利福尼亚州和工业界赞助。这项研究的核心是诸如智能尘埃之类的设备,它由加州大学伯克利分校的克里斯·皮斯特和他的同事开发。智能尘埃将无线通信传感器和信息细化节点结合在一个非常丰富的网络中。

Given my affiliation with a university known for its involvement with social issues, I firmly believe that the next drivers for the high-tech industry will involve the global interests of society. A consensus is forming that electronics has yet to penetrate application domains of great interest. Such potential applications are the focus at the Center for Information Technology Research in the Interest of Society, a very broad University of California program centered in Berkeley and sponsored by the State of California and industry. The central role in this research belongs to devices such as the Smart Dust, developed by Kris Pister and his colleagues at UC Berkeley. Smart Dust combines a wireless communication sensor and information elaboration node in a very rich network.

如果我们理所当然地认为这些应用将主导未来电子领域,那么 EDA 必须做些什么来支持它们呢?正如前面提到的,选择的设计风格应该有利于各种形式的重用,并且考虑到 NRE 和掩模成本的不断增加,使软件比现在更加普及。

If we take for granted that these applications will dominate the future landscape of electronics, what must EDA do to support them? As already mentioned, the design style of choice should favor reuse in all its forms and, given the constant increase in NRE and mask costs, make software even more pervasive than it is today.

临时通信协议也将在设计过程中发挥重要作用。在设计方法的历史上,设计生产力的变化总是与设计捕获抽象级别的提高有关。1971 年,也就是我毕业的那一年,IC 抽象的最高级别是晶体管原理图;10 年后是门。到 1990 年,HDL 已经普及,设计捕获处于寄存器传输级别。 图 4 显示了这些抽象级别的转变。

Ad hoc communication protocols will also play a substantial role in the design process. In the history of design methods, changes in design productivity were always associated with raising the level of abstraction in design capture. In 1971, the year I graduated, the highest level of IC abstraction was a transistor schematic; 10 years later it was the gate. By 1990, HDL was pervasive and design capture was at the register transfer level. Figure 4 shows these transitions in level of abstraction.

图 4.

提高抽象层次。

Raising the level of abstraction.

未来,EDA 必须使用比现在更粗粒度的块来提供所需的生产率提升。我们必须将系统级问题引入芯片设计中。用于描述系统的新语言(如 SystemC(由 Gupta、Liao 及其同事开创)和 System Verilog)的出现清楚地表明了这一趋势。然而,它们在解决更高抽象层次上的系统设计问题方面存在不足,主要是因为它们缺乏清晰、明确的综合语义。

In the future, EDA must work with blocks of much coarser granularity than today to provide the required productivity increase. We must bring system-level issues into chip design. The emergence of novel languages for the description of systems such as SystemC (pioneered by Gupta, Liao, and colleagues) and System Verilog are clear indications of this trend. However, they fall short in addressing the system design problem at higher levels of abstraction, mostly due to their lack of a clear, unambiguous synthesis semantics.

设计链支持

Support for the Design Chain

我已经谈论这些问题 15 年多了,但我仍然对它们充满热情。这段时间的趋势很明显:电子行业部门正在快速细分。系统公司已经缩减开支,回归产品规格和市场分析的核心竞争力,并将交付工程和系统组件的任务转移给其他公司。例如,爱立信和诺基亚等公司越来越少参与芯片设计。因此,半导体公司必须为他们的战略客户做更多的事情。一些工程职责已经转移。与此同时,半导体公司越来越依赖专业公司提供的知识产权,例如 ARM 提供处理器内核,Artist 提供库。一些制造业务已转移到 UMC、IBM 和台积电等公司。除了英特尔之外,这些都是将新技术推向市场的领导者。

I have been talking about these issues for more than 15 years, but I am still passionate about them. The trend has been clear over this time span: The electronics industry sector has been segmenting at a rapid pace. System companies have retrenched, returning to their core competencies of product specification and market analysis, and shifting to others the task of delivering the engineering and the system components. For example, companies like Ericsson and Nokia are increasingly less involved in chip design. Consequently, semiconductor companies must do more for their strategic customers. Some of the engineering responsibilities have transferred over. At the same time, semiconductor companies are increasingly relying on intellectual property provided by specialized companies, such as ARM for processor cores and Artist for libraries. Some manufacturing has transferred to companies like UMC, IBM, and TSMC. Aside from Intel, these are the leaders in bringing new technology to market.

SEMATECH 不断发展:全球产业研发协作新模式

SEMATECH Evolving: A New Model for Global Industrial R&D Coordination

肯尼斯·S·弗拉姆 德克萨斯大学奥斯汀分校

Kenneth S. Flamm University of Texas, Austin

20 世纪 70 年代末,全球半导体行业发生了翻天覆地的变化,而此前这一行业一直由美国制造商主导。日本推出了一系列政府与工业界合作的半导体研发联盟,即所谓的 VLSI 项目。大多数观察家认为,这些努力极大地提高了日本半导体制造商的技术和制造能力。

The late 1970s were a period of radical change in a global semiconductor industry previously dominated by US producers. Japan launched a series of government-industry semiconductor R&D consortia, the so-called VLSI projects. Most observers perceived these efforts to have greatly advanced the technological and manufacturing competence of Japanese semiconductor producers.

1987 年,美国国防部科学委员会发布报告指出,美国半导体制造商的相对地位迅速恶化,并称其为国家安全问题。作为回应,美国政府决定让国防部支付一个联合行业联盟 SEMATECH(半导体制造技术)的一半费用,该联盟每年的总预算为 2 亿美元。改进美国半导体制造技术的目标可能相当明确,但实现这一目标的方法引发了相当大的争论。在成立的最初几年里,SEMATECH 的组织重点发生了变化,而且并不总是完全有效。唯一不变的是,它仅限于美国公司——当日本制造商 NEC 于 1988 年寻求加入 SEMATECH 时,该组织拒绝了在美国设有生产工厂的日本制造商 NEC。

In 1987, the US Department of Defense's Science Board issued a report noting a rapid deterioration in the relative position of US semiconductor manufacturers, characterizing this as a national security issue. Responding, the US government decided to have the DoD pay half of the cost of a joint industry consortium dubbed SEMATECH (for semiconductor manufacturing technology), which had a total budget of$200 million annually. The objective of improving US semiconductor manufacturing technology might have been fairly clear, but the means of doing so sparked considerable debate. In its first few years of existence, SEMATECH's organizational focus shifted about, and it was not always wholly effective. One constant was that it was restricted to US companies—the organization turned away Japanese producer NEC, which had a US production plant, when NEC sought SEMATECH membership in 1988.

20 世纪 90 年代初,SEMATECH 重新调整了其结构和研究方向。早在几年前,该组织就越来越重视旨在改进美国半导体制造商从供应商处采购的设备和材料的项目。1992 年,在新任首席执行官威廉·斯宾塞的领导下,SEMATECH 进行了内部重组,并明确制定了一项新的长期战略(称为 SEMATECH II)。作为该计划的一部分,成员们的目标是大幅缩短将新技术节点引入制造厂的时间间隔。该战略的一个关键要素是美国半导体行业内所谓的路线图流程的制度化和接受——这是美国 IC 行业及其材料和设备供应商的主要参与者系统性地尝试

SEMATECH refocused its structure and research direction in the early 1990s. Even in earlier years, it had placed increasing emphasis on projects aimed at improving the equipment and materials that US semiconductor makers procured from suppliers. In 1992, under new CEO William Spencer, SEMATECH carried out an internal reorganization and explicitly defined a new long-range strategy (dubbed SEMATECH II). As part of this plan, members targeted a significant reduction in the elapsed time between introductions of new technology nodes into manufacturing plants. A crucial element in this strategy was the institutionalization and acceptance within the US semiconductor industry of a so-called roadmap process—a systematic attempt by the major players in both the US IC industry and its materials and equipment suppliers to

  • 共同制定制造下一代芯片可能所需的新技术的细节

  • jointly work out the details of likely new technologies required for manufacturing next-generation chips

  • 协调所需的引进时间,以及

  • coordinate the required timing for their introduction, and

  • 如果总体计划要取得成功,就必须加强对可能成为“障碍”并需要进一步研究的技术的研发力度。

  • intensify R&D efforts on technologies that were likely “showstoppers” and required further work if the overall schedule was to succeed.

1992 年,SEMATECH 监督发布了第一份国家半导体技术路线图。1994 年发布的第二份路线图仍然以大约每三年一次的历史速度引入新技术节点。但加快步伐的努力取得了成功:250 纳米技术节点比 1994 年路线图预测的提前一年上线。1997 年国家技术路线图要求保持两年间隔,而不是回到历史的三年模式,用于下一个技术节点(180 纳米)和后续技术节点。

SEMATECH oversaw the publication of the first such National Technology Roadmap for Semiconductors in 1992. The next one, issued in 1994, still had new technology nodes introduced at the historical pace of approximately every three years. But the effort to step up the pace succeeded: The 250-nm technology node came online a year earlier than predicted by the 1994 roadmap. The 1997 National Technology Roadmap called for maintaining the two-year interval, rather than returning to the historical three-year pattern, for the next technology node (180 nm) and those to follow.

在已全球化的半导体行业中,制造技术改进速度的加快显然得益于 SEMATECH 联盟之外的因素。全球竞争压力加剧;加快新技术部署速度是合乎逻辑的经济反应。然而,公开讨论全行业的研发需求以及通过全行业的计划明确协调各公司的研发工作是重大的新进展。

This acceleration in the rate of manufacturing technology improvement within what had become a globalized semiconductor industry clearly was assisted by factors beyond the walls of the SEMATECH consortium. Competitive pressures intensified around the world; the quickening pace of new technology deployment was a logical economic response. However, the open discussion of industry-wide R&D needs and explicit coordination of R&D efforts across companies through an industry-wide program were significant new developments.

整个行业都接受了以两年为周期的加速技术引进节奏,与此同时,SEMATECH 内部也发生了重大结构变化。1995 年,该联盟决定与外国生产商合作开展一个项目,以加快部署用于 300 毫米(12 英寸)硅片的材料和设备。1996 年,美国政府经双方同意终止了对 SEMATECH 的资助。1998 年,一个新的国际 SEMATECH 成立,以容纳越来越多涉及外国芯片生产商的项目。最终,在 1999 年,原 SEMATECH 重组为国际 SEMATECH。

The industry-wide embrace of an accelerated, two-year rhythm for technology introductions coincided with a major structural change within SEMATECH. In 1995, the consortium decided to join with foreign producers on a project to quicken the deployment of materials and equipment designed for use with 300-mm (12-inch) silicon wafers. The US government terminated its funding for SEMATECH in 1996 by mutual consent. A new International SEMATECH formed in 1998 to house the increasing number of projects involving foreign chip producers. Finally, in 1999, the original SEMATECH reorganized itself as International SEMATECH.

如今,SEMATECH 的活动与传统工业研究实验室的愿景大不相同。作为一个组织,它主要关注协调和标准:

Today, SEMATECH's activities little resemble the classical vision of an industrial research laboratory. As an organization, it is mainly concerned with coordination and standards:

  • 将材料和设备供应商与其成员聚集在一起,共同开展主要在其外部执行的技术项目。

  • bringing materials and equipment suppliers together with its members to work on technology projects largely executed outside its walls

  • 担任行业路线图的执行代理,以及

  • serving as executive agent for the industry roadmap, and

  • 联合众多公司来组织制造工具、软件和指标的行业标准。

  • uniting a broad array of firms to organize industry standards for tools, software, and metrics for manufacturing.

日本公司将 SEMATECH 视为一项重大成功。SEMATECH 模式(具有讽刺意味的是,这是美国对 20 世纪 70 年代日本 VLSI 联盟的反应)成为 20 世纪 90 年代中期新一代日本半导体研发联盟的灵感来源。日本半导体行业成立了自己的研发联盟 Selete,只有一个非日本成员,即韩国制造商三星。如今,国际半导体行业中共存着两个跨国研发组织:总部位于日本的 Selete 和总部位于美国的国际 SEMATECH。1997 年路线图成为最后一份国家技术路线图,取而代之的是国际技术路线图,由这两个全球研发联盟以及美国、欧洲、日本、韩国和台湾的半导体行业协会赞助和协调。

Companies in Japan viewed SEMATECH as a major success. The SEMATECH model (ironically, a US reaction to the Japanese VLSI consortia of the 1970s) became the inspiration for a new generation of Japanese semiconductor R&D consortia in the mid-1990s. Japan's semiconductor industry formed its own R&D consortium, Selete, with a single non-Japanese member, Korean producer Samsung. Today, two transnational R&D organizations coexist within the international semiconductor industry: Selete, headquartered in Japan; and International SEMATECH, headquartered in the US. The 1997 roadmap became the last nationaltechnology roadmap, replaced by the International Technology Roadmap, sponsored and coordinated through these two global R&D consortia, and semiconductor industry associations in the US, Europe, Japan, Korea, and Taiwan.

经济研究表明,在 20 世纪 90 年代末,采用两年周期与质量调整后的半导体价格加速下跌相吻合。半导体价格的快速下跌对计算机和通信设备的价格下跌产生了巨大影响。这反过来又对近年来的总体经济增长和生产率提高产生了重大影响。采用两年周期推出新技术节点仍然是近期路线图的一个特点,这些路线图继续呼吁在后来几年恢复到节奏较慢的三年周期。要求放慢周期的呼声大多没有得到回应。

Economic studies show that the move to a two-year cycle coincided with accelerating declines in quality-adjusted semiconductor prices in the late 1990s. Faster semiconductor price declines had a large impact on price declines for computer and communications equipment. These in turn had a major impact on aggregate economic growth and productivity improvement in recent years. The two-year cycle for the introduction of new technology nodes remains a feature of recent roadmaps, which continue to call for a reversion to the slower-paced three-year cycle in later years. Calls for a slower cycle have mainly gone unanswered.

在制定路线图之前,半导体公司根据戈登·摩尔的预测(每 18 个月每 IC 的晶体管数量将增加一倍)来组织技术规划。随着摩尔定律继续大致正确,各公司都围绕这一时间表组织技术计划。他们这样做并不是因为如果其他公司不按照相同的时间表进行创新,那么这个时间表必然能最大化他们的利润。相反,他们这样做是因为他们相信所有竞争对手都会按照摩尔定律的时间表推出新产品和新技术,他们也必须坚持这个计划才能保持竞争力。这种情况在 20 世纪 90 年代发生了变化,当时 SEMATECH 赞助了路线图协调机制,以追求其技术加速的目标。通过明确协调日益复杂的分散技术,需要同时改进以创建新一代制造系统,路线图似乎成功地改变了创新的节奏。事实上,该行业(迄今为止)未能成功摆脱“技术跑步机”并在本世纪末恢复到较慢的旧技术变革速度,这可能表明,一旦释放加速精灵,就很难再将其收回。一方面,如果一家公司将创新速度放慢到与行业其他公司相匹配的水平,它就不会获得竞争优势。另一方面,如果它放慢速度,而行业其他公司继续保持原来的更快速度,那么它就会损失惨重。

Before there was a roadmap, semiconductor companies organized their technology planning around something approximating Gordon Moore's prediction of a doubling of transistors per IC every 18 months. As Moore's law continued to be approximately true, companies organized technical plans around this timetable. They didn't do so because that schedule necessarily maximized their profit were everyone else not to innovate on the same timetable. Rather, they did so because they believed that all their competitors would introduce new products and technology on the Moore's law schedule, and they, too, had to stick to this plan to stay competitive. This changed in the 1990s, when SEMATECH sponsored the roadmap coordination mechanism in pursuing its goal of technology acceleration. By explicitly coordinating an increasingly complex array of decentralized pieces of technology, requiring simultaneous improvement to create a new generation of manufacturing systems, the roadmap appears to have succeeded in altering the tempo of innovation. In fact, the industry's unsuccessful (to date) efforts to get off the “technology treadmill” and return to an older, slower pace of technological change by the end of this decade might indicate that the acceleration genie, once unleashed, is not so easily put back into its bottle. On the one hand, an individual company gains no competitive advantage if it slows innovation to a level matched by the rest of the industry. On the other hand, it has a lot to lose if it slows down and the rest of the industry continues at the original, faster pace.

经济学家们通常认为技术变革的速度是外生的,是他们模型之外的自然产物。SEMATECH 故事的一个寓意是,技术变革的速度可能有一个与外部科学基础同样重要的内部政策因素。当一个行业必须精确协调从各种来源获得的许多复杂技术以创建经济上可行的新技术平台时,这一点尤其正确。预期甚至政治联盟等模糊而分散的因素可能会发挥重要作用。

Economists are largely accustomed to thinking of the speed of technological change as something that is exogenous, dropping in gracefully from outside their models. One moral of the SEMATECH story is that the pace of technological change might have an internal policy component as important as its external scientific foundations. This might be particularly true where an industry must precisely coordinate many complex items of technology secured from a broad variety of sources to create economically viable new technology platforms. Vague and diffuse factors like expectations and even political coalitions might then play an important role.

Kenneth S. Flamm 是德克萨斯大学奥斯汀分校林登·约翰逊公共事务学院国际事务系的 Dean Rusk 教授。他是一位经济学家,也是国际贸易和高科技产业投资方面的专家。联系他的邮箱是 kflamm@ mail.utexas.edu。

Kenneth S. Flamm holds the Dean Rusk Chair in International Affairs in the LBJ School of Public Affairs at the University of Texas, Austin. He is an economist and expert on international trade and investment in high-tech industries. Contact him at kflamm@ mail.utexas.edu.

在 PCB 领域,Solectron 和 Flextronics 等专业制造公司占据了制造的最大份额。支持这一趋势需要将设计视为一项跨公司边界的高度集成活动,而这项任务绝非易事。机械工程和电子、射频和微机电系统等工程学科的能力必须成为集成环境的一部分。这样的环境必须提供替代解决方案的经济分析以及一套能够揭示可用设计权衡的工具。EDA 必须支持具有严格语义的设计表示,这反过来又支持设计团队之间的清晰交接和更强大的设计验证方法。必须出现能够处理设计和制造数据的数据库。我们将这一新兴领域称为设计链支持,这是 EDA 整体上提高其在增值和经济机会方面的相关性的绝佳机会。为了应对这一挑战,我们必须将设计视为一门科学,而不是一套技术。

In PCBs, specialized manufacturing companies such as Solectron and Flextronics are taking in the lion's share of manufacturing. Supporting this movement requires viewing design as a highly integrated activity across company boundaries, a task that is far from easy. Competencies in engineering disciplines as distant as mechanical engineering and electronics, RF, and microelectro-mechanical systems, must become part of an integrated environment. Such an environment must provide an economic analysis of alternative solutions together with a set of tools capable of exposing the tradeoffs in available designs. EDA must support design representations with rigorous semantics, which in turn supports clean hand-offs between design teams and more robust design verification methods. Databases that can handle design and manufacturing data will have to emerge. We call this emerging field design-chain support, a great opportunity for EDA at large to increase its relevance both in terms of value added and economic opportunities. To respond to this challenge, we must think about design as a science instead of a set of technicalities.

平台作为一种“不透明”的抽象层,将下层的关键参数暴露给上层,在我看来,这是设计链支持设计方法的重要组成部分。我认为基于平台的设计是将系统从概念变为现实的一系列步骤。逻辑综合是从 RTL 到逻辑门抽象层应用范例的一个例子。从这个角度来看,我们限制自己实现的门库是低级平台,而 RTL 描述是顶级平台。选择最佳实现平台意味着使用库中的门来“覆盖” RTL 描述中的逻辑功能。

The concept of platform as an “opaque” layer of abstraction that exposes the critical parameters of the layers below to the layer above is, in my opinion, an essential part of a design methodology for design-chain support. I think of platform-based design as a sequence of steps that takes a system from concept to reality. Logic synthesis is an example of the paradigm applied from the RTL to the logicgate layer of abstraction. In this view, the library of gates that we limit ourselves to for implementation is the lower-level platform, and the RTL description is the top-level platform. Selecting the best implementation platform means using the gates in the library to “cover” the logic functions in the RTL description.

相反,考虑使用一个通用的语义域来表示堆栈中的顶层和底层抽象。在这种情况下,我们总是可以将最佳底层平台的选择公式化为覆盖问题。在我看来,我们社区的重点一直是“中间”层,这对应于 ASIC 设计方法。我们没有关注顶层(系统级抽象层)和底层,即电路设计和制造之间的联系。这两层是增加设计过程价值的最佳机会。

In contrast, consider using a common semantic domain to represent both the top and the bottom layer of abstraction in the stack. In this case, we can always formulate the selection of the best lower-level platform as a covering problem. In my view, our community's focus has been the “intermediate” level, which corresponds to the ASIC design methodology. We have not paid attention to the top level—the system-level layer of abstraction—and the bottom layer, the link between circuit design and manufacturing. These two layers are the best opportunities to add value to the design process.

SEMATECH 体验

The SEMATECH Experience

William J. Spencer,SEMATECH 国际公司

William J. Spencer, SEMATECH International

美国半导体行业于 1985 年被日本夺走了市场领导地位。自 20 世纪 70 年代末市场低迷以来,美国半导体行业经历了长达六年的衰退。

The US semiconductor industry lost its market leadership to Japan in 1985. This capped a six-year decline as the industry recovered from a market downturn in the late 1970s.

与此同时,美国半导体设备制造商的市场份额每年以约 5% 的速度被同一竞争对手夺走。尽管设备制造商在这两个行业领域开始衰退时拥有很大的市场份额,但到 20 世纪 80 年代末,它们注定会失去市场领导地位。此前,整个消费电子市场都离开了美国,因此许多人已经认为半导体市场最终也会有同样的命运。

At the same time, US semiconductor equipment manufacturers were losing market share to the same competitor at about 5% per year. Although equipment makers had a large market share at the start of this decline in both industry segments, they were destined to lose market leadership by the late 1980s. Earlier, the entire consumer electronics market had left the US, so many had already written off the semiconductor market as having the same eventual fate.

两个组织决定采取行动。美国国家半导体公司首席执行官查尔斯·斯波克领导下的半导体行业协会研究了扭转市场损失和导致市场损失的技术滞后的机会。马丁·玛丽埃塔公司首席执行官诺曼·奥古斯丁领导下的美国国防部委托国防科学委员会进行了一项研究,以衡量损失是否会造成国家安全问题。

Two groups decided to do something about this situation. The Semiconductor Industry Association under the leadership of Charles Sporck, CEO of National Semiconductor, examined opportunities for reversing the market loss and the technology lag that had led to it. The US Department of Defense under the leadership of Norman Augustine, CEO of Martin Marietta, commissioned a study by the Defense Science Board, measuring the loss in terms of whether it would create a national security issue.

这些研究结果促使半导体行业和一些政府机构商讨解决方案:政府和行业每年各出资 1 亿美元,组建一个专注于制造技术的联盟。该联盟的名称 SEMATECH 源自短语“半导体制造技术”。

The findings in these studies prompted the semiconductor industry and several government organizations to negotiate a proposed solution: The government and the industry would each provide$100 million per year to form a consortium to focus on manufacturing technology. The name for the consortium, SEMATECH, comes from the phrase semiconductor manufacturing technology.

这笔资金将支持最初由 14 名成员组成的联盟,以提升美国在半导体制造业中的地位。1987 年,在对拟议地点进行全国性审查后,新组织在德克萨斯州奥斯汀成立。技术人员来自成员公司,这些公司向 SEMATECH 派遣工程师,通常为期两年;SEMATECH 还雇佣了一些自己的全职员工。成员公司的工程师及其家人在任务期间搬到奥斯汀。经过一年的搜寻,英特尔的鲍勃·诺伊斯同意成为 SEMATECH 的第一任首席执行官。他于 1988 年 7 月加入了奥斯汀的新组织。

The money would support a consortium of originally 14 members to improve the US position in semiconductor manufacturing. After a nationwide review of proposed sites in 1987, the new organization set up home in Austin, Texas. The technical staff came from member companies that assigned engineers to SEMATECH, usually for a period of two years; SEMATECH also hired a few of its own full-time employees. The member companies' engineers and their families moved to Austin for the length of the assignment. After a yearlong search, Bob Noyce of Intel agreed to become SEMATECH's first CEO. He joined the new organization in Austin; that was in July 1988.

SEMATECH 为实现其使命奋斗了两年​​。旷日持久的讨论导致三家原始公司辞职,并选出了一位新的首席运营官,之后该组织开始专注于改进现有的半导体设备和开发新系统。资金主要来自 SEMATECH,开发通常在设备制造商的工厂进行。SEMATECH 工程师团队负责监督研发活动。这些计划需要成员公司委员会的批准,委员会定期在奥斯汀和设备公司所在地开会。计划参与者定期在委员会会议上报告他们的结果。

SEMATECH struggled with its mission for two years. The prolonged discussion led to the resignation of three of the original companies and the selection of a new chief operating officer, before the organization began focusing on improving current semiconductor equipment and developing new systems. The funding came principally from SEMATECH, with the development typically performed in the equipment manufacturers' facility. A team of SEMATECH engineers oversaw the R&D activity. These programs required approval from member company committees that met regularly in Austin and at the equipment company sites. Program participants regularly reported their results at committee meetings.

没有针对特定产品甚至特定产品的制造技术开展工作;SEMATECH 认为这是每个成员公司的竞争领域。设备改进项目的结果可供任何公司使用,无论是成员公司还是非成员公司,也无论是否为美国公司。唯一的限制是,在向非成员出售设备之前,必须满足成员公司对新设备或改进设备的要求。如果美国设备制造商要在全球半导体市场上竞争,向所有半导体制造商出售设备是必不可少的。

There was no work on specific products or even manufacturing techniques for specific products; SEMATECH considered this the competitive area for each member company. The results of the equipment improvement projects were available to any company, member or not, US or not. The only restriction was that the member companies' requirements for new or improved equipment be met before selling equipment to nonmembers. The sale to all semiconductor manufacturers was essential if US equipment manufacturers were to compete in the global semiconductor market.

到 1993 年,美国在半导体市场和设备市场的份额都发生了变化,两个行业都重回领导地位,这种情况一直持续到今天。关于 SEMATECH 在这一转变中的作用的问题不断出现。一些人认为其他因素——日本半导体市场的开放、美国和日本资本成本的变化、英特尔的复苏——也产生了一定的影响。几乎世界上所有主要的电视广播公司、报纸和杂志都来到奥斯汀,想知道发生了什么。《经济学人》对这一情况的报道可能最好是“美国半导体行业出现了重大复苏。许多人将一些功劳归功于 SEMATECH;没有人能证明他们没有发挥影响。”

The US share of both the semiconductor market and the equipment market had changed by 1993, and both industries returned to leadership positions, a situation that continues today. The question continually arises as to the role of SEMATECH in that turnaround. Some argue that other factors—the opening of the Japanese semiconductor market, changes in the cost of capital in the US and Japan, the resurgence of Intel—had some impact as well. Nearly every major TV broadcaster, newspaper, and magazine in the world descended on Austin to determine what had happened. Perhaps The Economist best reported the situation as “the US has had a major recovery in the semiconductor industry. Many give some credit to SEMATECH; no one can prove they didn't have an effect.”

无论 SEMATECH 在转型过程中发挥了什么作用,这项试验在其他经济领域都产生了类似的活动。它改变了各行业在开发新技术、制造工艺和合作方面进行研发的方式。

Whatever SEMATECH's role in the turnaround, the experiment generated similar activities in other economic areas. It has changed the way industries undertake R&D in developing new technology, manufacturing processes, and cooperative efforts.

1994 年,SEMATECH 自愿停止接受政府资助,该组织及其成员感谢政府在困难时期提供的帮助。他们表示,如果没有政府的帮助,就不可能实现转型。尽管政府在 1994 年之前每年提供 1 亿美元,但 SEMATECH 的管理和方向仍交给了成员。事实证明,这是一种独特而成功的方法。

When SEMATECH voluntarily ceased accepting government funding in 1994, the organization and its members thanked the government for its help in a difficult time. They expressed the opinion that the turnaround could not have been accomplished without government help. Although the government supplied$100 million per year until 1994, it left the management and direction of SEMATECH to the members. This proved to be a unique and successful approach.

William J. Spencer 已退休,是国际 SEMATECH 的名誉主席。他于 1990 年至 1997 年期间担任 SEMATECH 的首席执行官兼主席。联系他的邮箱是 spencerucb@yahoo.com。

William J. Spencer is retired and chairman emeritus of International SEMATECH. He served as SEMATECH's CEO and chairman from 1990 to 1997. Contact him at spencerucb@yahoo.com.

嵌入式系统设计

Embedded-System Design

在系统层面,我们应该密切关注嵌入式软件设计,将其视为创新的绝佳机会。过去六年来,DAC 的主题演讲指出了软件对于电子产品,甚至半导体行业的重要性。人们一致认为,我们需要改变软件设计方式,尤其是嵌入式软件。一些可怕的故事将非常昂贵的系统(如火星着陆器和阿丽亚娜火箭)的失败归因于软件错误。此外,Fabio Romeo 在 2001 年的 DAC 主题演讲小组中介绍了一个关于汽车行业嵌入式软件的有趣统计数据。在他的数据中,嵌入式软件的生产力范围为每天 6 到 10 行代码,具体取决于具体应用。这些公司记录了从项目开始到测试结束的生产力指标。然而,即使经过广泛的测试,该软件每百万行代码平均有 3,000 个错误。在访问了不同工业领域的几家公司后,我发现这种情况相当普遍。嵌入式软件的设计方法必须更加科学,将软件视为一种实施选择,而不是产品的一个孤立方面。

At the system level, we should look closely at embedded-software design as a great opportunity to innovate. For the past six years, keynotes at DAC pointed out the great importance of software for electronics, even for the semiconductor industry. There is consensus about the need to change the way we design software in general and embedded software in particular. Several horror stories trace the failure of very expensive systems, such as the Mars Lander and the Ariane rocket, to software bugs. In addition, Fabio Romeo, in a DAC keynote panel in 2001, presented an interesting statistic about embedded software for the automotive industry. In his data, productivity for embedded software ranged from 6 to 10 lines of code per day, depending on the specific application. These companies record productivity measures from the start of the project to the end of testing. However, even after extensive testing, this software has an average 3,000 errors per million lines of code. After visiting several companies in different industrial sectors, I find this situation to be quite common. The design methodology for embedded software must become more of a science and treat software as an implementation choice, not an isolated aspect of the product.

EDATech:推动半导体研究的未来创新

EDATech: Driving Future Innovations in Semicondutor Research

Fred Shlapak,摩托罗拉半导体产品部门

Fred Shlapak, Motorola Semiconductor Products Sector

过去四十年来,半导体工艺技术发展迅速。硅片生产率每 18 个月就会提高一次,而设计生产率则继续大幅落后。随着行业进入新纪元,我们面临的设计挑战已经有很多文章进行了探讨。 0.13 微米   时代。它们横跨数字和模拟领域。问题包括电源管理、功能验证、泄漏、超过 1.5 亿个晶体管设计的复杂性管理,以及以下的混合信号和数字设计 0.13 微米 . 名单还在继续。这些类型的艰巨挑战以前已经得到解决:没有人真正怀疑半导体技术人员会及时找到解决方案来满足或击败 电视 韋斯 预测。

Semiconductor process technology has been advancing at a tremendous pace over the last four decades. Silicon productivity is improving every 18 months, while design productivity continues to lag significantly. Much has been written about the design challenges we faced as the industry entered the 0.13 μm era. They spanned both digital and analog domains. Issues included power management, functional verification, leakage, complexity management for designs of more than 150 million transistors, and mixed-signal and digital design for below 0.13μm . The list goes on. These types of formidable challenges have been addressed before: No one really doubts that semiconductor technologists will find solutions in time to meet or beat the ITRS predictions.

证实这种信心和乐观情绪的证据来自这样一个事实:半导体行业继续通过有效的全行业合作伙伴关系在研发上投入数十亿美元。因此,尽管半导体技术成本不断上涨,但全球制造业的准入门槛已经降低,“耐心”的资金在亚洲市场创造了规模可观、竞争激烈的制造业。在我看来,随着亚洲的发展和繁荣,这种趋势将继续下去。(不这样认为完全是否认。)半导体制造商将在其商业模式中利用这一点,因为 12 英寸生产具有规模经济,而较小晶圆尺寸的晶圆成本较低。

The evidence validating this confidence and optimism stems from the fact that the semiconductor industry continues to spend billions of dollars on research and development through effective industry-wide partnerships. Consequently, even though semiconductor technology costs are increasing, the barriers of entry in manufacturing have been lowered on a global basis where “patient” money has created sizable, competitive manufacturing in the Asian marketplace. In my opinion, this trend will continue, as Asia grows and prospers. (Thinking otherwise is pure denial.) Semiconductor manufacturers will take advantage of this in their business models because of economies of scale in 12-inch production and lower wafer cost in smaller wafer dimensions.

为了快速推进工艺技术并避免成本重复,一些制造商已经建立了合作伙伴关系。飞利浦、摩托罗拉和意法半导体的合作伙伴关系就是一个例子,他们将开发 32 纳米节点的技术。随着时间的推移,将会出现更多这样的合作。

To make rapid advances in process technologies and avoid cost duplications, some manufacturers have formed partnerships. One example of this is the Philips, Motorola, and STMicroelectronics partnership, which will develop technology down to the 32-nm node. More cooperations like this will occur over time.

然而,在更高抽象层次上,设计生产力和设计技术效率仍然令人沮丧。其原因在于设计技术的生产者和消费者缺乏一致的行业努力。考虑到 EDA 行业的规模,这是一项艰巨的任务——也许不亚于半导体设备制造商面临的任务。

However, design productivity and design technology effectiveness at higher levels of abstractions remain dismal. The reason for this is lack of a concerted industry effort by both the producers and consumers of design technology. Given the EDA industry's size, this is a daunting task—perhaps no less than those facing semiconductor equipment manufacturers.

EDA 行业是否应该支持一套标准?答案是肯定的。在许多技术领域,硅系统工程方面的这种协同努力都是有价值的。这些包括设计工具的全球战略、可制造性设计、统计设计方法、低功耗设计和系统级验证。

Should the EDA industry support a set of standards? The answer is yes. There are many technical areas where such concerted effort in silicon systems engineering will be valuable. These include a global strategy for design tools, design for manufacturability, statistical design methods, low-power design, and system level validation.

鉴于当前和未来设计要求的复杂性,我相信,创建一个行业 EDA 联盟将使半导体行业及其客户受益,该联盟将制定行业标准,并提供创新源泉来满足不断变化的 IC 系统设计行业的需求——无论是无晶圆厂还是“轻晶圆厂”。美国目前在制造复杂系统芯片的技术方面处于领先地位;我们的挑战是建立一个工程生态系统,将其转化为长期的技术和经济优势。

With the complexities of current and future design requirements, I believe that the semiconductor industry and its customers would benefit by creating an industry EDA consortium that will set industry-wide standards and provide a source of innovation to feed the changing IC system design industry—be it fabless or “fablite.” The US currently has the lead in the know-how to build complex system chips; our challenge is to build an engineering ecosystem that turns this into a long-term technology and economic advantage.

弗雷德·什拉帕克 (Fred Shlapak) 曾任摩托罗拉半导体产品部门总裁兼首席执行官。

Fred Shlapak is past president and CEO of Motorola's Semiconductor Products Sector.

由于嵌入式软件的正确性通常与其时序行为有关,我们必须以某种方式将行为与实现平台联系起来;这意味着一种不同于传统范式的范式,后者小心地隐藏了计算引擎的细节。我们必须从整体上考虑嵌入式系统设计,而不是只关注嵌入式软件来解决问题!要做到这一点,教育体系必须改变,拓宽工程专业学生的背景,培养他们将嵌入式系统作为一个整体来考虑。我们需要同时设计硬件和软件的方法,而不是独立设计。软件开发人员必须处理表征硬件行为的参数。这样做将使他们能够预测与软件在实现平台上的执行相关的物理量;这些量包括时序、内存占用和功耗。反过来,硬件设计师必须知道什么对应用软件的正常工作很重要。

Since embedded software correctness often relates to its timing behavior, we must somehow link behavior to implementation platforms; this implies a different paradigm from the classical one, which carefully hides the computing engine's details. We must think of embedded-system design holistically, rather than focusing only on embedded software to solve the problem! To do so, the educational system must change, broadening the background of engineering students and training them to consider embedded systems as a whole. We need ways to design hardware and software concurrently but not independently. Software developers will have to deal with parameters that characterize the hardware's behavior. Doing so will permit them to predict physical quantities associated with the software's execution on the implementation platform; these quantities include timing, memory occupation, and power consumption. In turn, hardware designers must know what is important for the application software to work correctly.

面向制造的设计

Design for Manufacturing

特征尺寸的减小危及了电路设计和工艺开发之间的关注点分离。电路设计师再也不能忽略详细的物理效应对制造工艺的影响。随着最小特征尺寸缩小到光波长以下,掩模制作变得复杂,以解释光衍射图案。据估计,设计重新设计的比例高达 50%,这是无法容忍的。 0.13 μ 设计;这在一定程度上推迟了广泛采用 0.09 μ 技术节点。这种情况促使我们将抽象层结合起来,这样设计师就可以在电路设计中考虑制造,而制造也可以意识到设计的需求。

The decrease in feature size jeopardizes the separation of concerns between circuit design and process development. Circuit designers can no longer ignore the impact of detailed physical effects on the manufacturing process. As minimum feature sizes shrank below the wavelength of light, mask making became complex to account for the light diffraction patterns. Estimates point to an intolerable 50% in design re-spins for 0.13μm designs; this, in part, has delayed the widespread adoption of the 0.09μm technology node. The situation tempts us to combine layers of abstraction, so that designers account for manufacturing in circuit designs, and manufacturing is conscious of the needs of design.

然而,正如我之前所说,关注点分离对于设计效率和降低错误水平至关重要。因此,基于平台的设计原则也应该与此相关。我们必须确定制造应“导出”到设计的重要参数,以便电路设计师充分了解其选择的含义。设计师还应将他们需要满足的约束传播到制造层面,以确保设计能够正常工作。面向制造的设计将成为半导体行业和 EDA 行业的重要战场。

However, as I argued earlier, separation of concerns is essential for design productivity and lower error levels. Hence, platform-based design principles should be relevant at this level as well. We must identify the important parameters that manufacturing should “export” to design so that circuit designers are fully aware of the implications of their choices. Designers should also propagate the constraints that they need satisfied to the manufacturing level to ensure that the design will work correctly. Design for manufacturing will be an important battlefield for the semiconductor industry as well as for the EDA industry.

商业方面

Business Side

我概括了 EDA 在两个领域面临的巨大挑战。我认为 EDA 行业必须投入适当的注意力来扩大其业务范围,以涵盖这些领域。然而,当整体业务状况困难时,它必须这样做。创新是一项昂贵且有风险的提议,有时与中型上市公司的地位相冲突。其后果就是我们多年来所看到的:大型 EDA 公司掀起了一波并购浪潮。

I have outlined the grand challenges for EDA in two spaces. I believe the EDA industry must invest the right amount of attention to enlarge the business boundaries where it operates to embrace these spaces. However, it must do so when the overall business situation is difficult. Innovation is an expensive and risky proposition that sometimes clashes with the status of medium-sized public companies. The consequence is what we have seen over the years: a wave of mergers and acquisitions carried out by the major EDA companies.

正如 Smith-Barney 分析师 Robert Stern 几年前所说,“收购公司是这个行业进行研发的合法方式。”虽然我同意 Stern 的观点,但找到额外的创新机制也很重要。EDA 初创公司的创新是渐进式的,除了少数(尽管很重要)案例;成功的初创公司找到了更好的方法来做我们已经知道如何做的事情。此外,在这种经济环境下,大型公司在每股收益和资本化方面往往优于市场。风险投资处于四年的衰退期;IPO 窗口在 2001 年底关闭。从那时起到今天,没有一家 EDA 公司上市。2002 年,小公司的市场份额仅占整个 EDA 市场的 7.8%,并且正在失去优势。大型 EDA 公司的股价与纳斯达克市场保持一致,但小型公司的表现远逊于纳斯达克指数。

As Robert Stern, a Smith-Barney analyst said a few years ago, “Buying companies is a legitimate way of doing research and development in this industry.” Although I agree with Stern, it is also important to find additional mechanisms to innovate. The innovation from startups in EDA has been incremental, except for a few (albeit important) cases; successful startups found better ways to do things we already knew how to do. In addition, in this economic climate, larger companies tend to outperform the market in terms of both earnings per share and capitalization. Venture capital investment is in a four-year decline; the IPO window closed at the end of 2001. From then until today, not a single EDA company has gone public. In 2002, the market share of small companies was only 7.8% of the total EDA market and losing ground. The stock price of the large EDA companies aligned with the Nasdaq market, but the small-cap companies performed much worse than the Nasdaq index.

因此,尽管创业理念仍然有效,并且对于培育创新格局的重要组成部分至关重要,但我们需要新的方式来支持大规模创新。我们必须思考如何让创新在成熟公司内部“安全”。我们必须支持这样一种模式,即成熟公司的财务和商业实力与初创公司的充满活力的环境相结合。有想法的人必须能够创新,摆脱日常的苦差事,而这通常是任何企业环境中的典型情况。他们必须有激励措施和相关的责任感,从而提高成功的动力。然而,还需要更多更大胆的努力。

Thus, although the startup concept is still valid and necessary to foster an important part of the innovation landscape, we need new ways to support large-scale innovation. We must think about ways to make innovation “safe” inside established companies. We must support a model where the financial and commercial strength of an established company combine with the vibrant environment of a startup. People who have ideas must be able to innovate, free from the day-to-day drudgery that, in general, is typical of any corporate environment. They must have incentives with the associated accountability that make the motivation for success high. Yet additional bolder efforts are needed.

合作伙伴关系和 Edatech 理念

Partnering and the Edatech Concept

我认为供应商和客户之间的合作是缓解创新问题的重要途径。在英雄时代,这种合作非常有效。例如,我再怎么强调合作对 Cadence 和 Synopsys 的成功都不过分。创新合作应包括学术界,形成“良性三角”,这是 DeMan 首次提出并吹捧多年的。然而,我们在 DAC 上没有看到很多代表应用领域的系统工程师。我也没有看到工艺工程师。我们需要齐心协力将这些社区带到 DAC,使其成为 EDA 新时代的论坛。然而,这显然还不够。一些举措,如 Marco Focus 研究中心,将这三个群体聚集在一起,寻找设计电路的新方法,但我认为我们必须走得更远。

I see partnering between vendors and customers as an important way to alleviate the innovation problem. It has been very effective in the age of heroes. I cannot overemphasize the effects of partnerships in the success of Cadence and Synopsys, for example. Partnering for innovation should include academia, forming the “virtuous triangle,” which was first presented by DeMan and touted for many years. However, we have not seen many system engineers—representing the application domains—at DAC. Neither have I seen process engineers. We need a concerted effort to bring these communities to DAC to make it the forum for EDA's new age. However, this is clearly not enough. Some initiatives such as the Marco Focus Research Centers bring these three constituencies together to find new ways of designing circuits, but I believe we must go further.

我认为,由于资源不断流向中国和印度等远东国家,美国很有可能失去软件和电子系统设计的领导地位。尽管这种全球资源转移可能被视为积极因素,可以降低成本并提高盈利能力,但它可能会造成类似于我们在 20 世纪 80 年代所目睹的情况,当时 IC 制造业正快速从美国迁移(IC 制造业份额在几年内从 90% 暴跌至 40%)。当时许多人认为 IC 制造业是一种战略资源,业界应齐心协力改善美国的 IC 制造业,并保持设备行业的经济可行性。

I see a definite risk of the US losing leadership in software and electronic system design caused by a constant drain of resources toward Far East countries such as China and India. Although this global shift in resources might be seen as positive, reducing costs and increasing profitability, it might create a situation similar to the one that we have witnessed in the 1980s when IC manufacturing was migrating from the US at a fast rate (the share of IC manufacturing plummeted from 90% to 40% in a few years). Many argued then that IC manufacturing was a strategic resource and that the industry should mount a concerted effort to improve IC manufacturing in the US and to keep the equipment industry economically viable.

我认为 IC 和电子系统设计比制造更具战略意义。然而,随着电子系统和软件设计迁移到远东,我们不断失去工作机会和技术基础。在最近的一次演讲中(2003 年 10 月 6 日),英特尔的 Andy Grove 在华盛顿全球技术峰会上的演讲中独立描绘了一幅更为黯淡的软件现状图景。

I believe that IC and electronic system design are even more strategic than manufacturing. Yet we are constantly losing jobs and technical ground as electronic system and software design migrate to the Far East. In a recent presentation (6 October 2003), Andy Grove of Intel independently painted an even bleaker picture of the state of software in an address at the Global Technology Summit in Washington.

设备制造商对制造至关重要,而 EDA 对设计至关重要。鉴于目前的经济状况和行业结构,EDA 的地位与 1980 年代的设备公司相似。随着软件编程工作的迁移,它削弱了劳动力的智力构成,并大大增加了强大竞争对手出现的可能性。

As equipment manufacturers were essential for manufacturing, EDA is essential for design. Given the present economic conditions and industry structure, EDA is in a similar position as that of equipment companies in the 1980s. As software programming jobs migrate, it impoverishes the intellectual makeup of the workforce and considerably increases the likelihood of the emergence of strong competitors.

支持 EDATech:汇集资源,获得竞争优势

In Support of an EDATech: Pooling Resources for Competitive Advantage

雷·宾汉姆(Ray Bingham),Cadence

Ray Bingham, Cadence

创新是整个电子行业,尤其​​是 EDA 面临的巨大挑战。EDA 的创新有不同的形式:从方法和工具的渐进式发展,以提供更好、更快、更便宜的产品,到彻底改变设计方式的革命性主张。EDA 行业的主要参与者已经达到了难以敏捷和快速改变方向的程度。因此,创新通常是通过改进现有工具和方法、更有效地整合它们、提供服务以帮助部署它们以及收购拥有成熟技术的小型公司来实现的。这些小型公司传统上被认为是变革和创新的推动者。虽然这个角色当然非常适合初创公司,而且收购也很有效,但我认为我们不能仅仅依靠收购;我们需要在公司内部促进渐进式和革命性的创新。

Innovation is a grand challenge for the electronic industry in general and EDA in particular. Innovation in EDA comes in different flavors: from incremental evolution of methodologies and tools to provide better, faster, cheaper products to revolutionary propositions that change radically the way design is done. The major players in the EDA industry have reached a dimension that makes it difficult to be agile and change course rapidly. Hence, innovation is often brought about by improving existing tools and methodologies, integrating them more effectively, providing services to help in deploying them, and by acquiring smaller companies with proven technology. These smaller companies have been traditionally considered the agents of change and innovation. Although this role is certainly well suited for startups and acquisitions have been effective, I believe we cannot rely exclusively on acquisitions; we need to facilitate both evolutionary and revolutionary innovation inside our companies.

创新通常来自研究人员和技术人员的专注工作,他们全身心地投入到他们试图开发的技术中。在 EDA 公司的日常运营中,研究创新的整合仍然是一个问题。EDA 开发人员发现,在修复错误和添加功能方面支持现有工具需要大量的时间和精力。因此,我认为 EDA 行业需要实施一种机制,让拥有出色创新想法的人能够将他们的想法产品化,一方面,他们可以访问与现有产品相关的丰富软件基础,​​同时让他们免受与现有产品和客户群相关的开发和支持任务的影响。此外,如果他们的技术确实成功推向市场,我们必须找到一种奖励他们的方法。这个想法是重新创造创业公司的氛围和动力,而没有它的缺点。在 Cadence,我们实施了一个遵循这一总体思路的孵化模型,我们相信这种开发方法将产生 Alberto 在他的文章中倡导的实质性创新。

Innovation comes often from the dedicated work of researchers and technologists who devote their full, undivided attention to the technology they are trying to develop. In the day-to-day operation of EDA companies, integration of research innovation continues to be problematic. EDA developers find that supporting existing tools in terms of fixing bugs and adding features takes a significant amount of time and attention. Hence, I believe the EDA industry needs to implement a mechanism where people with brilliant, innovative ideas have a way of productizing them that, on one hand, provides access to the rich software base associated with existing products while at the same time shielding them from the development and support tasks associated with existing products and the installed base of customers. In addition, we must find a way of rewarding them if indeed their technology is successfully brought to market. The idea is to re-create the atmosphere and the motivation of a startup without its drawbacks. At Cadence, we have implemented an incubation model that follows this general idea, and we are confident this method of development will generate substantial innovation as advocated by Alberto in his article.

考虑到我们内部计划的成功,很明显,我们 EDA 需要一个可供整个行业使用的类似模型。我们需要推动行业发展到一个阶段,让所有参与者都能有效地进行创新,而不会浪费时间和财力去重新实现那些不会给产品带来附加值的技术。我们支持这一愿景的第一步是以开源形式向业界发布我们的第四代 EDA 数据库 Open Access。这项超过 2000 万美元的基础设施技术投资将帮助初创公司专注于他们的关键技术交付成果。因此,既降低了产品开发风险,又提供了一条顺利融入潜在客户设计环境的途径。在“EDATech:推动未来半导体研究创新”侧栏中,Fred Shlapak 描述了他牵头的一项计划,旨在与意法半导体和飞利浦合作,分担开发数字工艺生产线的巨额成本。这种方法清楚地表明,如果行业中的部分(如果不是全部)参与者采取战略立场并共享技术,那么他们就能取得很大成就,而这些技术不会给他们带来竞争优势,而如果这些技术是专有的,他们就必须承受开发和部署的费用。我提到了两个“竞争-合作”的例子,它们表明像我们这样的高科技行业可以如何提高将新创意推向市场的效率。现在的问题是,作为一个社区和一个相当大的工业部门,我们还能做些什么来提高我们在电子行业格局中的总体地位。特别是,我们如何首先为引擎提供动力来产生根本性的创新?

With the success of our internal program in mind, it is clear that we in EDA need a similar model available to the entire industry. We need to advance the industry to a stage where all players can be effective in innovating without losing time and financial resources to reimplement technology that does not bring value added to its products. Our first step in supporting this vision was to release our fourth-generation EDA database Open Access in an open source form to the industry. This donation of a more than$20million investment in infrastructure technology will help startups focus on their key technical deliverables. and, as a result, both reduce their risk in product development as well as provide a smooth integration path into potential customer design environments. In the “EDATech: Driving Future Innovations in Semiconductor Research” sidebar, Fred Shlapak describes an initiative he spearheaded to share the huge costs of developing manufacturing lines for digital processes in collaboration with STMicroelectronics and Philips. This approach is a clear indication that much can be accomplished if some (if not all) players of an industry take a strategic stance and share technology that will not give them a competitive advantage comparable to the expenses of development and deployment they will have to sustain if that technology were kept proprietary. I have mentioned two examples of “competitive-collaboration” that show how a high-technology industry such as ours can improve the effectiveness of bringing new ideas to market. The question now is what else can we do as a community and as a sizable industrial sector to improve our general position in the electronics industry landscape. In particular, how do we fuel the engine to produce radical innovation in the first place?

研究显然是创新的重要潜在来源,即使不是最重要的来源。持续研究是我们行业不能过分强调的一个战略层面。然而,进行能够带来设计和设计方法革命性变化的研究需要部署大量资源,而这些资源在短期甚至中期内都不会产生效益。风险很高,因为没有人能保证即使是最好的研究也能有效地推向市场以收回投资。这比电子行业其他部门的风险更大,因为设计方法不是精确的科学:在评估某种方法是否优于其他方法时,存在很大的主观因素。这带来了额外的不确定性,尤其是在严重的行业低迷时期,这使得资助研究变得具有挑战性。为了至少部分消除这种风险,确定优先事项并与竞争对手和客户共同评估想法无疑是重要的行动。

Research is clearly an important, if not the most important potential source of innovation. Sustaining research is a strategic dimension that our industry cannot overemphasize. Yet carrying out research that can yield a revolutionary change in design and design methodologies necessitates the deployment of significant resources that are not productive in the short and even medium term. The risk is high because there is no guarantee that even the best research will be taken effectively to market to repay the investment. This is even more so than for other sectors of the electronic industry, because design methodologies are not exact science: There are significant subjective factors in evaluating whether a given method is better than others. This aspect brings additional uncertainty that, especially in a severe industry downturn, makes funding research challenging. To eliminate this risk at least in part, defining priorities and evaluating ideas jointly with competitors and customers are definitely important actions.

全球化迫使各公司将制造甚至设计和软件转移到海外以保持竞争力。从长远来看,我们行业的知识基础可能会受到这种趋势的影响。EDATech 的提议必须得到 EDA 行业的支持。它将为 EDA 行业参与者和客户提供一个独特的机会,让他们能够在一个开放和协作的框架内合作。当然,要找到一种所有人都能接受的策略,还有很多问题需要解决(例如定义 IP 规则以及将结果转化为实际产品),但成功给行业带来的回报迫使我们去尝试。

Globalization is forcing companies to move manufacturing and even design and software offshore to remain competitive. The intellectual substrate of our industry can suffer from this trend in the long run. The proposal of an EDATech must be supported by the EDA industry. It will provide a unique opportunity for EDA industry players and customers to team up in an open and collaborative framework. Of course, there will be problems to solve to find a strategy that is acceptable to all (such as defining the rules for IP and the transfer of results into actual products) but the rewards to the industry in being successful compel us to try.

Ray Bingham 是 Cadence Design Systems 的总裁兼首席执行官。

Ray Bingham is president and CEO of Cadence Design Systems.

可以说,SEMATECH 通过在艰难时期持续创新,对保持 IC 和设备制造业的正常运转发挥了重要作用。为什么不将 EDATech 视为 EDA 行业的一种 SEMATECH 形式呢?EDA 领域对大规模创新的承诺还不够。EDA 行业需要基础设施来支持对革命性技术的风险投资。在 SEMATECH 中,政府和企业的重大努力为下一代生产线和设备奠定了基础,而这些生产线和设备面临着缺乏必要资金和投资的风险。如果没有 IC 和设备制造商之间的密切合作,实施在 SEMATECH 上测试的创新理念,这项努力就不可能取得成功。

Arguably SEMATECH had a strong impact in keeping IC and equipment manufacturing afloat by sustaining innovation in hard times. Why not think of an EDATech as a form of SEMATECH for the EDA industry? There is not enough commitment to large-scale innovation in the EDA space. The EDA industry needs an infrastructure to support risky investment in revolutionary technology. In SEMATECH, a major government and corporate effort provided the foundations for next-generation manufacturing lines and equipment that were at risk of falling short of the necessary funding and investment. The effort could not have succeeded without a strong collaboration between the IC and equipment manufacturers that implemented the innovative ideas tested at SEMATECH.

我希望业界和政府能够以相同的思路来看待 IC 设计和 EDA。这条路并非一帆风顺:我没有实施该计划的精确方案,但必须采取一些措施。要使 EDATech 这样的计划发挥作用,我们还需要 EDA 行业在共同的结构中共享技术、开发工作和研究成果。它还必须促进设计师和 EDA 专业人员之间的合作。

I would like the industry and the government to think along the same lines for IC design and EDA. The road is not without obstacles: I do not have a precise recipe for implementing this program, but something must be done. To make an initiative like EDATech work, we also need the EDA industry to share technology, development efforts, and research in a common structure. It also must foster collaborations among designers and EDA professionals.

多年来,我注意到 EDA 社区的设计专业知识显著减少。这种情况当然带来了困难,因为 EDA 公司不再能够“发明”新的设计方法,为设计人员提供显著的生产力提升。如今,IC 公司高管经常哀叹,他们面临着无法利用数十亿美元制造投资的风险,因为他们缺乏设计方法、工具和流程的适当支持。

I have noted over the years a notable reduction in design expertise in the EDA community. This situation is of course creating difficulties, because EDA companies are no longer capable of “inventing” new design methodologies that offer designers substantial productivity gains. Today, IC company executives often lament that they run the risk of not being able to leverage billions of dollars of manufacturing investments because they lack the appropriate support from design methodologies, tools, and flows.

EDA 是一个独特而美妙的领域,多年来,研究、创新和商业一直在这里融为一体,过去 40 年取得的成就就是明证。EDA 社区能否继续寻求更好的设计方法,将电子系统设计师的生产力提高几个数量级,同时提高质量?我相信可以,但这条路并不好走。我们面前还有许多困难。我呼吁供应商、客户和学术界之间有更深的紧迫感,建立更牢固的伙伴关系。

EDA IS A UNIQUE, wonderful field where research, innovation, and business have come together for many years, as demonstrated by its accomplishments over the past 40 years. Can the EDA community continue its quest for better design methodologies, increasing the productivity of electronic-system designers by orders of magnitude while also increasing quality? I believe so, but it is not an easy path. Many difficulties lay in front of us. I am calling for a deeper sense of urgency and for a stronger partnership among vendors, customers, and academia.

最后,我想引用维科的另一句名言(用我早已忘记的拉丁语随意翻译),我相信这句话会激励我们所有人。他将英雄时代描述为“对真理的神圣狂热,这种狂热存在于超越极限的永恒尝试中,存在于自我实现和超越自我的无限可能性中,以发现精神的力量并推动知识的新发展。”让我们努力实现这些话。

I would like to end with another quote by Vico (liberally translated using my long-forgotten Latin), which I believe will be a source of inspiration to us all. He characterized the age of heroes as “The holy furor for truth that lives in the eternal attempt to go beyond the limit, in the infinite possibility of self-realization and of overtaking ourselves to discover the power of the spirit and give a new push towards knowledge.” Let us make an effort to live up to these words.

Cites in Papers - IEEE (19)

选择全部
1 .
Giovanni De Micheli,“设计和技术中的奇怪循环:第 59 届 DAC 主题演讲”, IEEE 设计与测试 ,第 40 卷,第 5 期,第 96-103 页,2023 年。
2
Ebru Dalbudak、Karim Baratli、Yousef Fouzar、Bachir Lakhssassi、Karim El Guemhioui 和 Ahmed Lakhssassi,“使用敏捷方法在不同技术节点之间移植模拟和混合信号电路”, 2020 年 IEEE 国际物联网、电子和机电一体化会议(IEMTRONICS) ,第 1-7 页,2020 年。
3 .
王鑫,季晓峰,陆云平,李毅,周伟佳,张伟华,赵文云,“理解EDA算法的架构特征”, 2016年第45届国际并行处理会议(ICPP) ,第139-148页,2016年。
4 .
Andrew B. Kahng、Mulong Luo、Gi-Joon Nam、Siddhartha Nath、David Z. Pan 和 Gabriel Robins,“面向设计自动化研究影响的指标”, 2015 IEEE/ACM 国际计算机辅助设计会议 (ICCAD) ,第 263-270 页,2015 年。
5
Mickael Lanoe、Matteo Bordin、Dominique Heller、Philippe Coussy 和 Cyrille Chavet,“关键嵌入式系统设计的建模和代码生成框架:从 Simulink 到 VHDL 和 Ada/C 代码”, 2014 年第 21 届 IEEE 电子、电路和系统国际会议(ICECS) ,第 742-745 页,2014 年。
6 .
Sabah Al-Fedaghi、Noura Aljallal,“数字逻辑图的多级语义基础”, 2014 年第二届系统与信息学国际会议(ICSAI 2014) ,第 417-424 页,2014 年。
7
Monther Abusultan、Sunil P. Khatri,“通过全电源操作实现深亚阈值查找表设计”, 2014 IEEE 第 22 届现场可编程定制计算机国际研讨会 ,第 259-266 页,2014 年。
8
Alberto Sangiovanni-Vincentelli、Donatella Sciuto,“展望水晶球:从晶体管到智能地球”, IEEE 设计与测试 ,第 31 卷,第 2 期,第 47-55 页,2014 年。
9
Sam MH Ho、Steve CL Yuen、Hiu Ching Poon、Thomas CP Chau、Yan-Qing Ai、Philip HW Leong、Oliver CS Choy 和 Kong-Pang Pun,《结构化 ASIC:方法论与比较》, 2010 年现场可编程技术国际会议 ,第 377-380 页,2010 年。
10
Tomás G. Moreira、Marco A. Wehrmeister、Carlos E. Pereira、Jean-François Pétin 和 Eric Levrat,“嵌入式系统的自动代码生成:从 UML 规范到 VHDL 代码”, 2010 年第 8 届 IEEE 工业信息学国际会议 ,第 1085-1090 页,2010 年。
11
Salman Gopalani、Rajesh Garg、Sunil P Khatri、Mosong Cheng,“DFM 感知结构化 ASIC 设计”, 2009 年第 12 届国际集成电路研讨会论文集 ,第 29-32 页,2009 年。
12
Philippe Coussy、Daniel D. Gajski、Michael Meredith、Andres Takach,“高级综合简介”, IEEE 计算机设计与测试 ,第 26 卷,第 4 期,第 8-17 页,2009 年。
13
Giovanni De Micheli,“未来集成系统设计技术展望”, IEEE 集成电路与系统计算机辅助设计学报 ,第 28 卷,第 6 期,第 777-790 页,2009 年。
14
Kanupriya Gulati、Nikhil Jayakumar、Sunil P. Khatri,“使用传输晶体管逻辑的结构化 ASIC 设计方法”, 2007 IEEE 国际电路与系统研讨会 ,第 1787-1790 页,2007 年。
15
CP Ravikumar、R. Dandamudi、VR Devanathan、N. Haldar、K. Kiran 和 V. Kumar,“分布式和分层设计测试框架”, 第 18 届 VLSI 设计国际会议与第 4 届嵌入式系统设计国际会议联合举办 ,第 497-503 页,2005 年。
16
A. Hemani,“绘制 EDA 路线图”, IEEE 电路与器件杂志 ,第 20 卷,第 6 期,第 5-10 页,2004 年。
17
N. Jayakumar、SP Khatri,“使用 PLA 的金属和通孔掩模组可编程 VLSI 设计方法”, IEEE/ACM 国际计算机辅助设计会议,2004 年。ICCAD-2004。 ,第 590-594 页,2004 年。
18
Jeong-Taek Kong,“纳米硅片 CAD 设计挑战与成功”, IEEE 超大规模集成 (VLSI) 系统学报 ,第 12 卷,第 11 期,第 1132-1147 页,2004 年。
19
CP Ravikumar、G. Hetherington,“一种面向测试设计的整体并行和分层方法”, 2004 年国际测试会议 ,第 345-354 页,2004 年。

论文引用 - 其他出版商 (21)

Cites in Papers - Other Publishers (21)

1 .
Carliss Y. Baldwin,《设计规则,第 2 卷:第 13 章——半导体行业的缓慢变化结构》, SSRN 电子杂志 ,2021 年。
2
John D. Foley、Spencer Breiner、Eswaran Subrahmanian 和 John M. Dusel,“复杂系统设计规范、分析和综合的操作”,英国 皇家学会学报 A:数学、物理和工程科学版 ,第 477 卷,第 2250 期,第 20210099 页,2021 年。
3 .
Galia Marinova、Aida Bitri,“以电子设计自动化行业为重点的科技公司商业模式评估形式化评论”, IFAC-PapersOnLine ,第 54 卷,第 13 期,第 640 页,2021 年。
4 .
Luciano Lavagno、Grant Martin、Louis Scheffer,《 IC 系统设计、验证和测试的 EDA 概述》 ,第 1-1 页,2018 年。
5
Leon Stok、David Hathaway、Kurt Keutzer、David Chinnery,《设计流程》, IC 实施、电路设计和工艺技术的 EDA ,第 1-1 页,2018 年。
6 .
Evan Appleton、Douglas Densmore、Curtis Madsen 和 Nicholas Roehner,“生物设计自动化的需求和机遇:四个重点领域”,《 当前化学生物学观点》 ,第 40 卷,第 111 页,2017 年。
7
“设计流程”, IC实施、电路设计和工艺技术的电子设计自动化 ,第25页,2017年。
8
Alessandro Pinto、Alberto L. Sangiovanni Vincentelli,“CSL4P:一种平台合同规范语言”, 系统工程 ,第 20 卷,第 3 期,第 220 页,2017 年。
9
Luis Manuel Garcés Socarrás、Daniel Alejandro Romero Ares、Alejandro José Cabrera Sarmiento、Santiago Sánchez Solano、Piedad Brox Jiménez,“用于 FPGA 中图像直方图计算的自配置知识产权模块的基于模型的实现”, Ingeniería e Investigación ,第 37 卷,第 2 期,第 74 页,2017 年。
10
Luciano Lavagno、Grant E. Martin、Louis K. Scheffer 和 Igor L. Markov,《概述》, IC 系统设计、验证和测试的电子设计自动化 ,第 3 页,2017 年。
11
David Chinnery、Leon Stok、David Hathaway、Kurt Keutzer,《设计流程》, IC 实施、电路设计和工艺技术的电子设计自动化 ,第 3 页,2016 年。
12
J. Alexander Liddle、Gregg M. Gallatin,“纳米制造:一个视角”, ACS Nano ,第 10 卷,第 3 期,第 2995 页,2016 年。
13
“参考书目”, 自上而下的数字 VLSI 设计 ,第 553 页,2015 年。
14
“微电子学导论”, 自上而下的数字 VLSI 设计 ,第 1 页,2015 年。
15
Rajeev Alur、Thomas A. Henzinger、Moshe Y. Vardi,“系统设计和验证的实践理论”, ACM SIGLOG News ,第 2 卷,第 1 期,第 46 页,2015 年。
16
Matthew W. Lux、Brian W. Bramlett、David A. Ball 和 Jean Peccoud,“基因设计自动化:工程幻想还是科学复兴?”, 《生物技术趋势》 ,第 30 卷,第 2 期,第 120 页,2012 年。
17
Marcus Wagner,“探索还是利用?对大型企业收购的实证研究”, 《研究政策》 ,第 40 卷,第 9 期,第 1217 页,2011 年。
18
Fernando Abreu Gonçalves、José Figueiredo,《协商意义》,《 行动者网络理论与技术创新国际期刊》 ,第 2 卷,第 3 期,第 1 页,2010 年。
19
Diane E. Bailey、Paul M. Leonardi、Jan Chong,“注意差距:理解知识工作中的技术相互依赖和协调”, 组织科学 ,第 21 卷,第 3 期,第 713 页,2010 年。
20
Tomás G. Moreira、Marco A. Wehrmeister、Carlos E. Pereira、Jean-François Pétin 和 Eric Levrat,“从嵌入式系统的 UML 模型生成 VHDL 源代码”, 分布式、并行和生物启发系统 ,第 329 卷,第 125 页,2010 年。
21
Jonathan A. Goler、Brian W. Bramlett 和 Jean Peccoud,《基因设计:超越序列》, 《生物技术趋势》 ,第 26 卷,第 10 期,第 538 页,2008 年。